CPRI Intel® FPGA IP User Guide

ID 683595
Date 7/01/2022

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

5. CPRI Intel® FPGA IP Core Registers

The CPRI IP core internal registers are accessible using the CPU interface, an Avalon-MM interface which conforms to the Avalon Interface Specifications.

All of these registers are 32 bits wide and the addresses are shown as hexadecimal byte address values. The registers can be accessed on a 32-bit (4-byte) basis. The addressing for the registers therefore increments by units of 4.

Write access to a Reserved or undefined location has no effect. Read accesses to a Reserved or undefined location return an undefined result.

Refer to the device specific PHY User Guides for information about the PHY registers.

Table 53.  Register Access CodesLists the access codes used to describe the type of register bits.
Code Description
RW Read / write
RO Read only
RC Read to clear
UR0 Reserved —undefined result on read, no effect on write