CPRI Intel® FPGA IP User Guide

ID 683595
Date 7/01/2022

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2.5. Integrating Your Intel® FPGA IP Core in Your Design: Required External Blocks

You must connect your CPRI Intel® FPGA IP to some additional required design components. Your design can simulate and compile without some of these connections and logical blocks, but it will not function correctly in hardware unless all of them are present and connected in your design.

The CPRI IP core requires that you define, instantiate, and connect the following additional software and hardware modules for all CPRI IP variations:

  • An external transceiver PLL IP core to drive the TX transceiver clock. You must instantiate the TX PLL IP core in software separately from the CPRI IP core. In Intel® Arria® 10 and Intel® Stratix® 10 devices, this requirement supports the configuration of multiple IP cores using the same transceiver block in the device.
  • One or more external reset controllers to coordinate the reset sequence for the CPRI IP core in your design.

In addition, some IP core variations require additional modules to function correctly in hardware.

  • CPRI link slave modules require an off-chip clean-up PLL.
  • Variations that target a 28-nm device (Arria V, Arria V GZ, Cyclone V, or Stratix V device family) require an external Transceiver Reconfiguration Controller Intel FPGA IP.
  • Variations with the single-trip delay calibration feature require additional blocks that Intel® provides but does not connect in your design.
Figure 6. Required External BlocksAn example showing how you could connect required components to a single CPRI Intel® FPGA IP core that target V-series, Intel® Arria® 10 and Intel® Stratix® 10 L- and H-tile devices.