Intel® Arria® 10 Native Fixed Point DSP IP Core User Guide

ID 683583
Date 3/13/2017
Document Table of Contents

1.1. Arria 10 Native Fixed Point DSP IP Core Features

The Arria 10 Native Fixed Point DSP IP Core supports the following features:

  • High-performance, power-optimized, and fully registered multiplication operations
  • 18-bit and 27-bit word lengths
  • Two 18 × 19 multipliers or one 27 × 27 multiplier per DSP block
  • Built-in addition, subtraction, and 64-bit double accumulation register to combine multiplication results
  • Cascading 19-bit or 27-bit when pre-adder is disabled and cascading 18-bit when pre-adder is used to form the tap-delay line for filtering applications
  • Cascading 64-bit output bus to propagate output results from one block to the next block without external logic support
  • Hard pre-adder supported in 19-bit and 27-bit modes for symmetric filters
  • Internal coefficient register bank in both 18-bit and 27-bit modes for filter implementation
  • 18-bit and 27-bit systolic finite impulse response (FIR) filters with distributed output adder