Intel® Arria® 10 Native Fixed Point DSP IP Core User Guide

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ID 683583
Date 3/13/2017
Public
Document Table of Contents
Document Table of Contents x
1. Intel® Arria® Native Fixed Point DSP IP Core User Guide 2. Getting Started 3. Functional Description A. Arria 10 Native Fixed Point DSP IP Core User Guide Document Archives B. Additional Information
1. Intel® Arria® Native Fixed Point DSP IP Core User Guide x
1.1. Arria 10 Native Fixed Point DSP IP Core Features
2. Getting Started x
2.1. Arria 10 Native Fixed Point DSP IP Core Parameter Settings
2.1. Arria 10 Native Fixed Point DSP IP Core Parameter Settings x
2.1.1. Operation Mode Tab 2.1.2. Pre-adder Tab 2.1.3. Internal Coefficient Tab 2.1.4. Accumulator/Output Cascade Tab 2.1.5. Pipelining Tab 2.1.6. Maximum Input Data Width Per Operation Mode
3. Functional Description x
3.1. Operational Modes 3.2. Optional Modules 3.3. Clocking Scheme 3.4. Arria 10 Native Fixed Point DSP IP Core Signals
3.1. Operational Modes x
3.1.1. The 18 × 18 Full Mode 3.1.2. The 18 × 18 Sum of 2 Mode 3.1.3. The 18 × 18 Plus 36 Mode 3.1.4. The 18 × 18 Systolic Mode 3.1.5. The 27 × 27 Mode
3.1.3. The 18 × 18 Plus 36 Mode x
3.1.3.1. Using Less Than 36-bit Operand In 18 × 18 Plus 36 Mode
3.2. Optional Modules x
3.2.1. Input Cascade 3.2.2. Pre-adder 3.2.3. Internal Coefficient 3.2.4. Accumulator and Output Cascade 3.2.5. Pipeline Register
B. Additional Information x
B.1. Arria 10 Native Fixed Point DSP IP Core Document Revision History
1. Intel® Arria® Native Fixed Point DSP IP Core User Guide
2. Getting Started
3. Functional Description
A. Arria 10 Native Fixed Point DSP IP Core User Guide Document Archives
B. Additional Information

1.1. Arria 10 Native Fixed Point DSP IP Core Features

The Arria 10 Native Fixed Point DSP IP Core supports the following features:

  • High-performance, power-optimized, and fully registered multiplication operations
  • 18-bit and 27-bit word lengths
  • Two 18 × 19 multipliers or one 27 × 27 multiplier per DSP block
  • Built-in addition, subtraction, and 64-bit double accumulation register to combine multiplication results
  • Cascading 19-bit or 27-bit when pre-adder is disabled and cascading 18-bit when pre-adder is used to form the tap-delay line for filtering applications
  • Cascading 64-bit output bus to propagate output results from one block to the next block without external logic support
  • Hard pre-adder supported in 19-bit and 27-bit modes for symmetric filters
  • Internal coefficient register bank in both 18-bit and 27-bit modes for filter implementation
  • 18-bit and 27-bit systolic finite impulse response (FIR) filters with distributed output adder
Level Two Title