Intel® Arria® 10 Native Fixed Point DSP IP Core User Guide

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ID 683583
Date 3/13/2017
Public

3.1.5. The 27 × 27 Mode

When configured as 27 × 27 mode, the Arria 10 Native Fixed Point DSP IP core enables a 27(signed/unsigned) × 27(signed/unsigned) multiplier. The output bus can support up to 64 bits with accumulator/output cascade enabled. This mode applies the equation of resulta = ax * ay.
Figure 6. The 27 × 27 Mode Architecture

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