Intel® Arria® 10 Native Fixed Point DSP IP Core User Guide

Download
ID 683583
Date 3/13/2017
Public

2.1.5. Pipelining Tab

Table 5.  Pipelining Tab
Parameter IP Generated Parameter Value Description
Add input pipeline register to the input data signal (x/y/z/coefsel) input_pipeline_clock

No

Clock0

Clock1

Clock2

Select Clock0, Clock1 or Clock2 to enable and specify the input clock signal for x, y, z, coefsela and coefselb pipeline input registers.
Add input pipeline register to the 'sub' data signal sub_pipeline_clock

No

Clock0

Clock1

Clock2

Select Clock0, Clock1 or Clock2 to enable and specify the input clock signal for the sub pipeline input register. 2
Add input pipeline register to the 'accumulate' data signal accum_pipeline_clock

No

Clock0

Clock1

Clock2

Select Clock0, Clock1 or Clock2 to enable and specify the input clock signal for the accumulate pipeline input register.2
Add input pipeline register to the 'loadconst' data signal load_const_pipeline_clock

No

Clock0

Clock1

Clock2

Select Clock0, Clock1 or Clock2 to enable and specify the input clock signal for the loadconst pipeline input register.2
Add input pipeline register to the 'negate' data signal negate_pipeline_clock

No

Clock0

Clock1

Clock2

Select Clock0, Clock1 or Clock2 to enable and specify the input clock signal for the negate pipeline input register.2
2 All pipeline input registers for dynamic control signals must have the same clock setting.

Did you find the information on this page useful?

Characters remaining:

Feedback Message