Intel® Arria® 10 Native Fixed Point DSP IP Core User Guide

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ID 683583
Date 3/13/2017
Public

3.2.5. Pipeline Register

The Arria 10 Native Fixed Point DSP IP core supports a single level of pipeline register. The pipeline register supports up to three clock sources and one asynchronous clear signal to reset the pipeline registers. There are five pipeline registers:
  • data input bus pipeline register
  • sub dynamic control signal pipeline register
  • negate dynamic control signal pipeline register
  • accumulate dynamic control signal pipeline register
  • loadconst dynamic control pipeline register

You can choose to enable each data input bus pipeline registers and the dynamic control signal pipeline registers independently. However, all enabled pipeline registers must use the same clock source.

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