Intel® Arria® 10 Native Fixed Point DSP IP Core User Guide

Download
ID 683583
Date 3/13/2017
Public

B.1. Arria 10 Native Fixed Point DSP IP Core Document Revision History

Table 15.  Document Revision History

Date

Version

Changes

March 2017 2017.03.13 Rebranded as Intel.
June 2016 2016.06.10
  • Added Enable 'sub' port, Enable 'accumulate' port, Enable 'negate' port, and Enable 'loadconst' port parameters in the Arria 10 Native Fixed Point DSP IP Core Parameter table.
  • Changed Enable output cascade with chainin port parameter to Enable chainin port parameter.
  • Clarified that bz[] signal is not supported in m27x27 operational mode.
  • Added Arria 10 Native Fixed Point DSP IP Core Document Archives section.
November 2015 2015.11.06
  • Updated 'ax' operand source and 'bx operand source descriptions in Internal Coefficient Tab parameter table.
  • “Changed instances of Quartus II to Quartus Prime.
  • Added related links to Introduction to Altera IP Cores, Creating Version-Independent IP and Qsys Simulation Scripts, and Project Management Best Practices.
December 2014 2014.12.19 Initial release.

Did you find the information on this page useful?

Characters remaining:

Feedback Message