Intel® Arria® 10 Native Fixed Point DSP IP Core User Guide

ID 683583
Date 3/13/2017
Document Table of Contents

3.1.4. The 18 × 18 Systolic Mode

In 18 × 18 systolic operational mode, the Arria 10 Native Fixed Point DSP IP core enables the top and bottom multipliers, an input systolic register for the top multiplier and a chainin systolic register for the chainin input signals. When you enable output cascade, this mode supports resulta output width of 44 bits. When you enable accumulator feature without output cascade, you can configure the resulta output width to 64 bits.

Figure 5. The 18 × 18 Systolic Mode Architecture