Intel® Arria® 10 Native Fixed Point DSP IP Core User Guide

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ID 683583
Date 3/13/2017
Public

2.1.1. Operation Mode Tab

Table 1.  Operation Mode Tab
Parameter IP Generated Parameter Value Description
Please choose the operation mode operation_mode

m18×18_full

m18×18_sumof2

m18×18_plus36

m18×18_systolic

m27×27

Select the desired operational mode.
Multiplier Configuration
Representation format for top multiplier x operand signed_max

signed

unsigned

Specify the representation format for the top multiplier x operand.
Representation format for top multiplier y operand signed_may

signed

unsigned

Specify the representation format for the top multiplier y operand.
Representation format for bottom multiplier x operand signed_mbx

signed

unsigned

Specify the representation format for the bottom multiplier x operand.
Representation format for bottom multiplier y operand signed_mby

signed

unsigned

Specify the representation format for the bottom multiplier y operand.

Always select unsigned for m18×18_plus36 .

Enable 'sub' port enable_sub No

Yes

Select Yes to enable sub port.
Register input 'sub' of the multiplier sub_clock

No

Clock0

Clock1

Clock2

Select Clock0, Clock1 or Clock2 to enable and specify the input clock signal for sub input register.
Input Cascade
Enable input cascade for 'ay' input ay_use_scan_in

No

Yes

Select Yes to enable input cascade module for ay data input.

When you enable input cascade module, the Arria 10 Native Fixed Point DSP IP core uses the scanin input signals as input instead of ay input signals.

Enable input cascade for 'by' input by_use_scan_in

No

Yes

Select Yes to enable input cascade module for by data input.

When you enable input cascade module, the Arria 10 Native Fixed Point DSP IP core uses the ay input signals as input instead of by input signals.

Enable data ay delay register delay_scan_out_ay

No

Yes

Select Yes to enable delay register between ay and by input registers.

This feature is not supported in m18×18_plus36 and m27x27 operational mode.

Enable data by delay register delay_scan_out_by

No

Yes

Select Yes to enable delay register between by input registers and scanout output bus.

This feature is not supported in m18×18_plus36 and m27x27 operational mode.

Enable scanout port scanout_enable

No

Yes

Select Yes to enable scanout output bus.
'scanout' output bus width scan_out_width 1–27 Specify the width of scanout output bus.
Data 'x' Configuration
'ax' input bus width ax_width 1–27 Specify the width of ax input bus. 1
Register input 'ax' of the multiplier ax_clock

No

Clock0

Clock1

Clock2

Select Clock0, Clock1 or Clock2 to enable and specify the input clock signal for ax input register.

ax input register is not available if you set 'ax' operand source to 'coef'.

'bx' input bus width bx_width 1–18 Specify the width of bx input bus.1
Register input 'bx' of the multiplier bx_clock

No

Clock0

Clock1

Clock2

Select Clock0, Clock1 or Clock2 to enable and specify the input clock signal for bx input register.

bx input register is not available if you set 'bx' operand source to 'coef'.

Data 'y' Configuration
'ay' or 'scanin' bus width ay_scan_in_width 1–27 Specify the width of ay or scanin input bus.1
Register input 'ay' or input 'scanin' of the multiplier ay_scan_in_clock

No

Clock0

Clock1

Clock2

Select Clock0, Clock1 or Clock2 to enable and specify the input clock signal for ay or scanin input register.
'by' input bus width by_width 1–19 Specify the width of by input bus.1
Register input 'by' of the multiplier by_clock

No

Clock0

Clock1

Clock2

Select Clock0, Clock1 or Clock2 to enable and specify the input clock signal for by or scanin input register.1
Output 'result' Configuration
'resulta' output bus width result_a_width 1–64 Specify the width of resulta output bus.
'resultb' output bus width result_b_width 1–64 Specify the width of resultb output bus.
Use output register output_clock

No

Clock0

Clock1

Clock2

Select Clock0, Clock1 or Clock2 to enable and specify the input clock signal for resulta and resultb output registers.

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