Intel® Arria® 10 Native Fixed Point DSP IP Core User Guide

ID 683583
Date 3/13/2017
Document Table of Contents

3.1.3. The 18 × 18 Plus 36 Mode

When configured as 18 × 18 Plus 36 mode, the Arria 10 Native Fixed Point DSP IP core enables only the top multiplier. This mode applies the equation of resulta = (ax * ay) + az.
Figure 4. The 18 × 18 Plus 36 Mode Architecture

You must set Representation format for bottom multipliers y operand to unsigned when using this mode. When the input bus is less than 36-bit in this mode, you are required to provide the necessary signed extension to fill up the 36-bit input.