JESD204B Intel® FPGA IP User Guide

Download PDF
ID 683442
Date 7/20/2023
Public
Document Table of Contents
Document Table of Contents x
1. JESD204B IP Quick Reference 2. About the JESD204B Intel® FPGA IP 3. Getting Started 4. JESD204B IP Functional Description 5. JESD204B IP Deterministic Latency Implementation Guidelines 6. JESD204B IP Debug Guidelines 7. JESD204B Intel® FPGA IP User Guide Archives 8. Document Revision History for the JESD204B Intel® FPGA IP User Guide
2. About the JESD204B Intel® FPGA IP x
2.1. Release Information 2.2. Device Family Support 2.3. Datapath Modes 2.4. IP Variation 2.5. JESD204B IP Configuration 2.6. Channel Bonding 2.7. Performance and Resource Utilization
2.5. JESD204B IP Configuration x
2.5.1. Run-Time Configuration
3. Getting Started x
3.1. Introduction to Intel® FPGA IP Cores 3.2. Installing and Licensing Intel® FPGA IP Cores 3.3. Intel® FPGA IP Evaluation Mode 3.4. Upgrading IP Cores 3.5. IP Catalog and Parameter Editor 3.6. Design Walkthrough 3.7. JESD204B Design Examples 3.8. JESD204B IP Design Considerations 3.9. JESD204B Intel® FPGA IP Parameters 3.10. JESD204B IP Component Files 3.11. JESD204B IP Testbench
3.6. Design Walkthrough x
3.6.1. Creating a New Intel® Quartus® Prime Project 3.6.2. Parameterizing and Generating the IP 3.6.3. Compiling the JESD204B IP Core Design 3.6.4. Programming an FPGA Device
3.8. JESD204B IP Design Considerations x
3.8.1. Integrating the JESD204B IP in Platform Designer 3.8.2. Pin Assignments 3.8.3. Adding External Transceiver PLLs 3.8.4. Timing Constraints For Input Clocks
3.11. JESD204B IP Testbench x
3.11.1. Generating and Simulating the IP Testbench 3.11.2. Testbench Simulation Flow
3.11.1. Generating and Simulating the IP Testbench x
3.11.1.1. Generating the Testbench Simulation Model 3.11.1.2. Simulating the IP Testbench
4. JESD204B IP Functional Description x
4.1. Transmitter 4.2. Receiver 4.3. Operation 4.4. Clocking Scheme 4.5. Reset Scheme 4.6. Signals 4.7. Registers
4.1. Transmitter x
4.1.1. TX Data Link Layer 4.1.2. TX PHY Layer
4.1.1. TX Data Link Layer x
4.1.1.1. TX CGS 4.1.1.2. TX ILAS 4.1.1.3. User Data Phase
4.2. Receiver x
4.2.1. RX Data Link Layer 4.2.2. RX PHY Layer
4.2.1. RX Data Link Layer x
4.2.1.1. RX CGS 4.2.1.2. Frame Synchronization 4.2.1.3. Frame Alignment 4.2.1.4. Lane Alignment 4.2.1.5. ILAS Data 4.2.1.6. Initial Lane Synchronization
4.3. Operation x
4.3.1. Operating Modes 4.3.2. Scrambler/Descrambler 4.3.3. SYNC_N Signal 4.3.4. Link Reinitialization 4.3.5. Link Startup Sequence 4.3.6. Error Reporting Through SYNC_N Signal
4.3.1. Operating Modes x
4.3.1.1. Subclass 0 Operating Mode 4.3.1.2. Subclass 1 Operating Mode 4.3.1.3. Subclass 2 Operating Mode
4.4. Clocking Scheme x
4.4.1. Device Clock 4.4.2. Link Clock 4.4.3. Local MultiFrame Clock 4.4.4. Clock Correlation 4.4.5. Transceiver Calibration Clock Source
4.5. Reset Scheme x
4.5.1. Reset Sequence 4.5.2. ADC–FPGA Subsystem Reset Sequence 4.5.3. FPGA–DAC Subsystem Reset Sequence
4.6. Signals x
4.6.1. Transmitter Signals 4.6.2. Receiver Signals
4.7. Registers x
4.7.1. Register Access Type Convention 4.7.2. Transmitter Registers 4.7.3. Receiver Registers
5. JESD204B IP Deterministic Latency Implementation Guidelines x
5.1. SYSREF Guidelines 5.2. Constraining Incoming SYSREF Signal 5.3. Programmable RBD Offset 5.4. Programmable LMFC Offset 5.5. Maintaining Deterministic Latency during Link Reinitialization
6. JESD204B IP Debug Guidelines x
6.1. Clocking Scheme 6.2. JESD204B Parameters 6.3. SPI Programming 6.4. Converter and FPGA Operating Conditions 6.5. Signal Polarity and FPGA Pin Assignment 6.6. Creating a Signal Tap Debug File to Match Your Design Hierarchy 6.7. Debugging JESD204B Link Using System Console
6.6. Creating a Signal Tap Debug File to Match Your Design Hierarchy x
6.6.1. Removing Irrelevant Signals and Adding E-Tile PHY Signals
1. JESD204B IP Quick Reference
2. About the JESD204B Intel® FPGA IP
3. Getting Started
4. JESD204B IP Functional Description
5. JESD204B IP Deterministic Latency Implementation Guidelines
6. JESD204B IP Debug Guidelines
7. JESD204B Intel® FPGA IP User Guide Archives
8. Document Revision History for the JESD204B Intel® FPGA IP User Guide

4.6.2. Receiver Signals

Figure 25. Receiver Signal DiagramL denotes the number of lanes.
Table 26.  Receiver Signals

Signal

Width

Direction

Description

Clocks and Resets
pll_ref_clk

1

Input

Transceiver reference clock signal.

rxlink_clk

1

Input

RX link clock signal used by the Avalon® streaming interface. This clock is equal to RX data rate divided by 40.

For Subclass 1, you cannot use the output of rxphy_clk signal as rxlink_clk signal. To sample SYSREF correctly, the core PLL must provide the rxlink_clk signal and must be configured as normal operating mode.

rxlink_rst_n_reset_n

1

Input

Reset for the RX link clock signal. This reset is an active low signal.

rxphy_clk[]

L

Output

Recovered clock signal. This clock is derived from the clock data recovery (CDR) and the frequency depends on the JESD204B IP core data rate.

  • For PCS option in Hard PCS or Soft PCS mode, this clock has the same frequency as the rxlink_clk signal.
  • For PCS option in PMA Direct mode, this clock is half the frequency of rxlink_clk signal.
rx_digitalreset[] 33

L

Input

Reset for the transceiver PCS block. This reset is an active high signal.

Note: This signal is not applicable for Intel Agilex® 7 and Intel® Stratix® 10 E-tile devices.
rx_digitalreset_stat[] L Output TX PCS digital reset status port connected to the transceiver reset controller.
Note: This signal is applicable only for Intel® Stratix® 10 L-tile and H-tile devices.
rx_analogreset[] 33

L

Input

Reset for the CDR and transceiver PMA block. This reset is an active high signal.

Note: This signal is not applicable for Intel Agilex® 7 and Intel® Stratix® 10 E-tile devices.
rx_analogreset_stat[] L Output TX PMA analog reset status port connected to the transceiver reset controller.
Note: This signal is applicable only for Intel® Stratix® 10 L-tile and H-tile devices.
rx_islockedtodata[] 33

L

Output

This signal is asserted to indicate that the RX CDR PLL is locked to the RX data and the RX CDR has changed from LTR to LTD mode.

rx_cal_busy[] 33

L

Output

RX calibration in progress signal. This signal is asserted to indicate that the RX transceiver calibration is in progress.

Note: This signal is not applicable for Intel Agilex® 7 and Intel® Stratix® 10 E-tile devices.

Signal

Width

Direction

Description

Transceiver Interface
rx_serial_data[]

L

Input

Differential high-speed serial input data. The clock is recovered from the serial data stream.

rx_serial_data_n

L

Input

Differential high-speed serial input data. The clock is recovered from the serial data stream.

Note: This signal is applicable only for Intel Agilex® 7 and Intel® Stratix® 10 E-tile devices.
reconfig_to_xcvr[]

L*70

Input

Dynamic reconfiguration input for the hard transceiver.

This signal is only applicable for for Arria V, Cyclone V, and Stratix V devices.

You must connect these signals to the Transceiver Reconfiguration Controller IP core regardless of whether run-time reconfiguration is enabled or disabled. The Transceiver Reconfiguration Controller IP core also supports various calibration function during transceiver power up.

reconfig_from_xcvr[]

L*46

Output

Dynamic reconfiguration output for the hard transceiver.

This signal is only applicable for for Arria V, Cyclone V, and Stratix V devices

You must connect these signals to the Transceiver Reconfiguration Controller IP core regardless of whether run-time reconfiguration is enabled or disabled. The Transceiver Reconfiguration Controller IP core also supports various calibration function during transceiver power up.

reconfig_clk

reconfig_clk[]

reconfig_clk_ch<0..L-1>

  • 1 if Share Reconfiguration Interface = On
  • L if Share Reconfiguration Interface = Off and Provide Separate Reconfiguration Interface for Each Channel = Off
  • 1 bit per channel port if Share Reconfiguration Interface = Off and Provide Separate Reconfiguration Interface for Each Channel = On

Input

The Avalon® memory-mapped clock input. The frequency range is 100–125 MHz.

This signal is only available if you enable dynamic reconfiguration for Intel® Arria® 10, Intel® Cyclone® 10 GX, and Intel® Stratix® 10 devices.

reconfig_reset

reconfig_reset[]

reconfig_reset_ch<0..L-1>

  • 1 if Share Reconfiguration Interface = On
  • L if Share Reconfiguration Interface = Off and Provide Separate Reconfiguration Interface for Each Channel = Off
  • 1 bit per channel port if Share Reconfiguration Interface = Off and Provide Separate Reconfiguration Interface for Each Channel = On

Input

Reset signal for the Transceiver Reconfiguration Controller IP core. This signal is active high and level sensitive.

This signal is only available if you enable dynamic reconfiguration for Intel® Arria® 10, Intel® Cyclone® 10 GX, and Intel® Stratix® 10 devices.

reconfig_avmm_address[]

reconfig_avmm_address_ch<0..L-1>[]

Intel® Arria® 10 and Intel® Cyclone® 10 GX

  • log2L*1024 if Share Reconfiguration Interface = On
  • 10*L if Share Reconfiguration Interface = Off and Provide Separate Reconfiguration Interface for Each Channel = Off
  • 10 bits per channel port if Share Reconfiguration Interface = Off and Provide Separate Reconfiguration Interface for Each Channel = On

Intel® Stratix® 10

  • log2L*2048 if Share Reconfiguration Interface = On
  • 11*L if Share Reconfiguration Interface = Off and Provide Separate Reconfiguration Interface for Each Channel = Off
  • 11 bits per channel port if Share Reconfiguration Interface = Off and Provide Separate Reconfiguration Interface for Each Channel = On

Input

The Avalon® memory-mapped address.

This signal is only available if you enable dynamic reconfiguration for Intel® Arria® 10, Intel® Cyclone® 10 GX, and Intel® Stratix® 10 devices.

reconfig_avmm_writedata[]

reconfig_avmm_writedata_ch<0..L-1>[]

For all devices except Intel Agilex® 7 and Intel® Stratix® 10 E-tile.

  • 32 if Share Reconfiguration Interface = On
  • 32*L if Share Reconfiguration Interface = Off and Provide Separate Reconfiguration Interface for Each Channel = Off
  • 32 bits per channel port if Share Reconfiguration Interface = Off and Provide Separate Reconfiguration Interface for Each Channel = On

For Intel Agilex® 7 and Intel® Stratix® 10 E-tile devices.

  • 8 if Share Reconfiguration Interface = On
  • 8*L if Share Reconfiguration Interface = Off and Provide Separate Reconfiguration Interface for Each Channel = Off
  • 8 bits per channel port if Share Reconfiguration Interface = Off and Provide Separate Reconfiguration Interface for Each Channel = On

Input

The input data.

This signal is only available if you enable dynamic reconfiguration for Intel® Arria® 10, Intel® Cyclone® 10 GX, and Intel® Stratix® 10 devices.

reconfig_avmm_readdata[]

reconfig_avmm_readdata_ch<0..L-1>[]

For all devices except Intel Agilex® 7 and Intel® Stratix® 10 E-tile.

  • 32 if Share Reconfiguration Interface = On
  • 32*L if Share Reconfiguration Interface = Off and Provide Separate Reconfiguration Interface for Each Channel = Off
  • 32 bits per channel port if Share Reconfiguration Interface = Off and Provide Separate Reconfiguration Interface for Each Channel = On

For Intel Agilex® 7 and Intel® Stratix® 10 E-tile devices.

  • 8 if Share Reconfiguration Interface = On
  • 8*L if Share Reconfiguration Interface = Off and Provide Separate Reconfiguration Interface for Each Channel = Off
  • 8 bits per channel port if Share Reconfiguration Interface = Off and Provide Separate Reconfiguration Interface for Each Channel = On

Output

The output data.

This signal is only available if you enable dynamic reconfiguration for Intel® Arria® 10, Intel® Cyclone® 10 GX, and Intel® Stratix® 10 devices.

reconfig_avmm_write

reconfig_avmm_write[]

reconfig_avmm_write_ch<0..L-1>

  • 1 if Share Reconfiguration Interface = On
  • L if Share Reconfiguration Interface = Off and Provide Separate Reconfiguration Interface for Each Channel = Off
  • 1 bit per channel port if Share Reconfiguration Interface = Off and Provide Separate Reconfiguration Interface for Each Channel = On

Input

Write signal. This signal is active high.

This signal is only available if you enable dynamic reconfiguration for Intel® Arria® 10, Intel® Cyclone® 10 GX, and Intel® Stratix® 10 devices.

reconfig_avmm_read

reconfig_avmm_read[]

reconfig_avmm_read_ch<0..L-1>

  • 1 if Share Reconfiguration Interface = On
  • L if Share Reconfiguration Interface = Off and Provide Separate Reconfiguration Interface for Each Channel = Off
  • 1 bit per channel port if Share Reconfiguration Interface = Off and Provide Separate Reconfiguration Interface for Each Channel = On

Input

Read signal. This signal is active high.

This signal is only available if you enable dynamic reconfiguration for Intel® Arria® 10, Intel® Cyclone® 10 GX, and Intel® Stratix® 10 devices.

reconfig_avmm_waitrequest

reconfig_avmm_waitrequest[]

reconfig_avmm_waitrequest_ch<0..L-1>

  • 1 if Share Reconfiguration Interface = On
  • L if Share Reconfiguration Interface = Off and Provide Separate Reconfiguration Interface for Each Channel = Off
  • 1 bit per channel port if Share Reconfiguration Interface = Off and Provide Separate Reconfiguration Interface for Each Channel = On

Output

Wait request signal.

This signal is only available if you enable dynamic reconfiguration for Intel® Arria® 10, Intel® Cyclone® 10 GX, and Intel® Stratix® 10 devices.

phy_rx_ready L Output

Signal to indicate the transceiver RX is ready.

Note: This signal is applicable only for Intel Agilex® 7 and Intel® Stratix® 10 E-tile devices.
phy_rx_pma_ready L Output

Signal to indicate the transceiver RX PMA is ready. This signal must be asserted before you assert or deassert any RX resets.

Note: This signal is applicable only for Intel Agilex® 7 and Intel® Stratix® 10 E-tile devices.
phy_rx_rst_n 1 Input

Active-high hard reset signal that resets the transceiver RX interface.

Asserting this signal does not reset the transceiver PMA. Refer to the E-tile Transceiver PHY User Guide about how to reset PMA through the Avalon® memory-mapped reconfiguration interface.

Note: This signal is applicable only for Intel Agilex® 7 and Intel® Stratix® 10 E-tile devices.

Signal

Width

Direction

Description

Avalon® Streaming Interface
jesd204_rx_link_data[]

L*32

Output

Indicates a 32-bit data from the DLL to the transport layer. The data format is big endian, where the earliest octet is placed in bit [31:24] and the latest octet is placed in bit [7:0].

jesd204_rx_link_valid

1

Output

Indicates whether the data to the transport layer is valid or invalid. The Avalon® streaming source interface in the RX core cannot be backpressured and transmits the data when the jesd204_rx_data_valid signal is asserted.

  • 0—data is invalid
  • 1—data is valid
jesd204_rx_link_ready

1

Input

Indicates that the Avalon® streaming sink interface in the transport layer is ready to receive data.

jesd204_rx_frame_error

1

Input

Indicates an empty data stream due to invalid data. This signal is asserted high to indicate an error during data transfer from the RX core to the transport layer.

Signal

Width

Direction

Description

Avalon® Memory-Mapped Interface
jesd204_rx_avs_clk

1

Input

The Avalon® memory-mapped interface clock signal. This clock is asynchronous to all the functional clocks in the JESD204B IP core. The JESD204B IP core can handle any cross clock ratio and therefore the clock frequency can range from 75 MHz to 125 MHz.

jesd204_rx_avs_rst_n

1

Input

This reset is associated with the jesd204_rx_avs_clk signal. This reset is an active low signal. You can assert this reset signal asynchronously but must deassert it synchronously to the jesd204_rx_avs_clk signal. After you deassert this signal, the CPU can configure the CSRs.

jesd204_rx_avs_chipselect

1

Input

When this signal is present, the slave port ignores all Avalon® memory-mapped signals unless this signal is asserted. This signal must be used in combination with read or write. If the Avalon® memory-mapped bus does not support chip select, you are recommended to tie this port to 1.

jesd204_rx_avs_address[]

8

Input

For Avalon® memory-mapped slave, the interconnect translates the byte address into a word address in the address space so that each slave access is for a word of data. For example, address = 0 selects the first word of the slave and address = 1 selects the second word of the slave.

jesd204_rx_avs_writedata[]

32

Input

32-bit data for write transfers. The width of this signal and the jesd204_rx_avs_readdata[31:0] signal must be the same if both signals are present.

jesd204_rx_avs_read

1

Input

This signal is asserted to indicate a read transfer. This is an active high signal and requires the jesd204_rx_avs_readdata[31:0] signal to be in use.

jesd204_rx_avs_write

1

Input

This signal is asserted to indicate a write transfer. This is an active high signal and requires the jesd204_rx_avs_writedata[31:0] signal to be in use.

jesd204_rx_avs_readdata[]

32

Output

32-bit data driven from the Avalon® memory-mapped slave to master in response to a read transfer.

jesd204_rx_avs_waitrequest

1

Output

This signal is asserted by the Avalon® memory-mapped slave to indicate that it is unable to respond to a read or write request. The JESD204B IP core ties this signal to 0 to return the data in the access cycle.

Signal

Width

Direction

Description

JESD204 Interface
sysref

1

Input

SYSREF signal for JESD204B Subclass 1 implementation.

For Subclass 0 and Subclass 2 mode, tie-off this signal to 0.

dev_sync_n

1

Output

Indicates a SYNC~ from the receiver. This is an active low signal and is asserted 0 to indicate a synchronization request. Instead of reporting the link error through this signal, the JESD204B IP core uses the jesd204_rx_int signal to interrupt the CPU.

For multilink synchronization, you can optionally connect the DEV_SYNC_N from each IP core to the input of an AND gate. The output of the AND gate is exported to the FPGA pins for connection to the analog-to-digital converters. Refer to AN803 and AN804 for more information about the connection guidelines.

sof[]

4

Output

Indicates a start of frame.

  • [3]—start of frame for jesd204_rx_link_data[31:24]
  • [2]—start of frame for jesd204_rx_link_data[23:16]
  • [1]—start of frame for jesd204_rx_link_data[15:8]
  • [0]—start of frame for jesd204_rx_link_data[7:0]
somf[]

4

Output

Indicates a start of multiframe.

  • [3]—start of multiframe for jesd204_rx_link_data[31:24]
  • [2]—start of multiframe for jesd204_rx_link_data[23:16]
  • [1]—start of multiframe for jesd204_rx_link_data[15:8]
  • [0]—start of multiframe for jesd204_rx_link_data[7:0]
dev_lane_aligned

1

Output

Indicates that all lanes for this device are aligned.

alldev_lane_aligned

1

Input

Aligns all lanes for this device.

For multidevice synchronization, input all the dev_lane_aligned signals to an AND gate and connect the AND gate output to this pin.

For single device support, connect the dev_lane_aligned signal back to this signal.

Signal

Width

Direction

Description

CSR
csr_l[]

5

Output

Indicates the number of active lanes for the link. The transport layer can use this signal as a run-time parameter.

csr_f[]

8

Output

Indicates the number of octets per frame. The transport layer can use this signal as a run-time parameter.

csr_k[]

5

Output

Indicates the number of frames per multiframe. The transport layer can use this signal as a run-time parameter.

csr_m[]

8

Output

Indicates the number of converters for the link. The transport layer can use this signal as a run-time parameter.

csr_cs[]

2

Output

Indicates the number of control bits per sample. The transport layer can use this signal as a run-time parameter.

csr_n[]

5

Output

Indicates the converter resolution. The transport layer can use this signal as a run-time parameter.

csr_np[]

5

Output

Indicates the total number of bits per sample. The transport layer can use this signal as a run-time parameter.

csr_s[]

5

Output

Indicates the number of samples per converter per frame cycle. The transport layer can use this signal as a run-time parameter.

csr_hd

1

Output

Indicates the high density data format. The transport layer can use this signal as a run-time parameter.

csr_cf[]

5

Output

Indicates the number of control words per frame clock period per link. The transport layer can use this signal as a run-time parameter.

csr_lane_powerdown[]

L

Output

Indicates which lane is powered down. You need to set this signal if you have configured the link and want to reduce the number of active lanes.

Signal

Width

Direction

Description

Out-of-band (OOB)
jesd204_rx_int

1

Output

Interrupt pin for the JESD204B IP core. Interrupt is asserted when any error is detected. Configure the rx_err_enable register to set the type of error that can trigger an interrupt.

Signal

Width

Direction

Description

Debug or Testing
jesd204_rx_dlb_data[]

L*32

Input

Optional signal for parallel data to the DLL in TX to RX loopback testing. 34
csr_rx_testmode[]

4

Output

Indicates the test mode for the JESD204B IP core and the test pattern for the test pattern checker in the design example.

Note: The test pattern checker is a component of the design example and is not a part of the JESD204B IP core.

Refer to the rx_test register in the register map.

jesd204_rx_dlb_data_valid[]

L

Input

Optional signal to indicate valid data for each byte in TX to RX loopback testing. 34
jesd204_rx_dlb_kchar_data[]

L*4

Input

Optional signal to indicate the K character value for each byte in TX to RX loopback testing. 34

jesd204_rx_dlb_errdetect[]

L*4

Input

Optional signal to indicate 8B/10B error. 34
jesd204_rx_dlb_ disperr[]

L*4

Input

Optional signal to indicate running disparity. 34
Related Information
33 The Transceiver PHY Reset Controller IP Core controls this signal.
34 This signal is only for internal testing purposes. Tie this signal to low.
Level Two Title