JESD204B Intel® FPGA IP User Guide

ID 683442
Date 7/20/2023
Document Table of Contents

4.4.5. Transceiver Calibration Clock Source

Intel® Stratix® 10 L-tile, H-tile, and E-tile and Intel Agilex® 7 E-tile devices use the OSC_CLK_1 pin to provide the transceiver calibration clock source.

You must provide a 25, 100, or 125 MHz free-running and stable clock to the OSC_CLK_1 pin. The FPGA device's Internal Oscillator cannot be used for transceiver calibration. Do not select this clock source as the Configuration clock source in the Intel® Quartus® Prime software settings. For Intel® Stratix® 10 L-tile and H-tile devices, refer to the Calibration section in the L- and H-Tile Transceiver PHY User Guide.

To change the configuration clock source, follow these steps:
  1. Open your project in the Intel® Quartus® Prime software.
  2. Right-click the device part number in your Intel® Quartus® Prime project.
  3. Select Device, and click on Device and Options.
  4. Select General from the Category pane.
  5. Select 25 MHz OSC_CLK_1 pin, 125 MHz OSC_CLK_1 pin, or 100 MHz OSC_CLK_1 pin from the Configuration clock source drop-down list.
  6. Click OK.
Note: A critical warning message appears in the Intel® Quartus® Prime software if you do not select any of the options for the Configuration clock source parameter.