JESD204B Intel® FPGA IP User Guide

ID 683442
Date 7/20/2023
Document Table of Contents Lane Alignment

After the frame synchronization phase has entered FS_DATA, the lane alignment is monitored via /A/ character (/K28.3/) at the end of multiframe. The first /A/ detection in the ILAS phase is important for the RX core to determine the minimum RX buffer release for inter-lane alignment. There are two types of error that is detected in lane alignment phase:

  • Arrival of /A/ character from multiple lanes exceed one multiframe.
  • Misalignment detected during user data phase.

The realignment rules for lane alignment are similar to frame alignment:

  • If two successive and valid /A/ characters are detected at the same position other than the assumed end of multiframe—without receiving a valid/invalid /A/ character at the expected position between two /A/ characters—the receiver aligns the lane to the position of the newly received /A/ characters.
  • If a recent frame alignment causes the loss of lane alignment, the receiver realigns the lane frame—which is already at the position of the first received /A/ character—at the unexpected position.