The JESD204B IP core supports a basic one clock cycle transaction bus. There is no support for burst mode and wait-state feature (the avs_waitrequest signal is tied to 0). The JESD204B IP core Avalon® memory-mapped slave interface has a data width of 32 bits and is implemented based on word addressing. The Avalon® memory-mapped slave interface does not support byte enable access.
Each write transfer has a writeWaitTime of 0 cycle while a read transfer has a readWaitTime of 1 cycle and readLatency of 1 cycle.
All registers that are Read-Writable must be protected to comply with Security Development Lifecycle (SDL) practices. You are required to perform the register access protection.
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