2. About the JESD204B Intel® FPGA IP
The JESD204B IP incorporates:
- Media access control (MAC)—data link layer (DLL) block that controls the link states and character replacement.
- Physical layer (PHY)—physical coding sublayer (PCS) and physical media attachment (PMA) block.
The JESD204B IP does not incorporate the Transport Layer (TL) that controls the frame assembly and disassembly. The TL and test components are provided as part of a design example component where you can customize the design for different converter devices.
- Data rate of up to 19.2 Gbps (characterization up to 12.5 G)
- Run-time JESD204B parameter configuration (L, M, F, S, N, K, CS, CF)
- MAC and PHY partitioning for portability
- Subclass 0 mode for backward compatibility to JESD204A
- Subclass 1 mode for deterministic latency support (using SYSREF) between the ADC/DAC and logic device
- Subclass 2 mode for deterministic latency support (using SYNC_N) between the ADC/DAC and logic device
- Multi-device synchronization
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