JESD204B Intel® FPGA IP User Guide

ID 683442
Date 7/20/2023
Document Table of Contents

3.6.2. Parameterizing and Generating the IP

Refer to Parameters for the IP core parameter values and description.

  1. In the IP Catalog (Tools > IP Catalog), locate and double-click the JESD204B Intel® FPGA IP.
  2. Specify a top-level name for your custom IP variation. This name identifies the IP core variation files in your project. If prompted, also specify the target Intel® FPGA device family and output file HDL preference. Click OK.
  3. In the Main tab, set the following options:
    • Jesd204b wrapper
    • Data path
    • Jesd204b subclass
    • Data Rate
    • Transceiver Tile
    • PCS Option
    • PLL Type
    • Bonding Mode
    • PLL/CDR Reference Clock Frequency
    • Enable Bit reversal and Byte reversal
    • Enable Transceiver Dynamic Reconfiguration
    • Enable Native PHY Debug Master Endpoint
    • Enable Capability Registers
    • Set user-defined IP identifier
    • Enable Control and Status Registers
    • Enable PRBS Soft Accumulators
  4. In the Jesd204b Configurations tab, select the following configurations:
    • Common configurations (L, M, Enable manual F configuration, F, N, N', S, K)
    • Advanced configurations (SCR, CS, CF, HD, ECC_EN, PHADJ, ADJCNT, ADJDIR)
  5. In the Configurations and Status Registers tab, set the following configurations:
    • Device ID
    • Bank ID
    • Lane ID
    • Lane checksum
  6. After parameterizing the core, go to the Example Design tab and click Generate Example Design to create the simulation testbench. Skip to 8 if you do not want to generate the design example.
  7. Set a name for your <example_design_directory> and click OK to generate supporting files and scripts.
    The testbench and scripts are located in the <example_design_directory>/ip_sim folder.

    The Generate Example Design option generates supporting files for the following entities:

    • IP core for simulation—refer to Generating and Simulating the IP Testbench
    • IP core design example for simulation—refer to Generating and Simulating the Design Example section in the respective design example user guides.
    • IP core design example for synthesis—refer to Compiling the JESD204B IP Core Design Example section in the respective design example user guides.
  8. Click Finish or Generate HDL to generate synthesis and other optional files matching your IP variation specifications. The parameter editor generates the top-level .ip, .qip or .qsys IP variation file and HDL files for synthesis and simulation.

    The top-level IP variation is added to the current Intel® Quartus® Prime project. Click Project > Add/Remove Files in Project to manually add a .qip or .qsys file to a project. Make appropriate pin assignments to connect ports.

Note: Some parameter options are grayed out if they are not supported in a selected configuration or it is a derived parameter.