JESD204B Intel® FPGA IP User Guide

ID 683442
Date 7/20/2023
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4.4.2. Link Clock

The device clock is the timing reference for the JESD204B system.

Due to the clock network architecture in the FPGA, JESD204B IP core does not use the device clock to clock the SYSREF signal because the GCLK or RCLK is not fully compensated. You are recommended to use the PLL Intel® FPGA IP core (in Arria V, Cyclone V, and Stratix V devices) or IOPLL Intel® FPGA IP core (in Intel® Arria® 10, Intel® Cyclone® 10 GX, and Intel® Stratix® 10 devices) to generate both the link clock and frame clock. The PLL Intel® FPGA IP core must operate in normal mode or source synchronous mode and uses a dedicated reference clock pin as the input reference clock source to achieve the following state:

  • the GCLK and RCLK clock network latency is fully compensated.
  • the link clock and frame clock at the registers are phase-aligned to the input of the clock pin.

To provide consistency across the design regardless of frame clock and sampling clock, the link clock is used as a timing reference.

The PLL Intel® FPGA IP core should provide both the frame clock and link clock from the same PLL as these two clocks are treated as synchronous in the design.

For Subclass 0 mode, the device clock is not required to sample the SYSREF signal edge. The link clock does not need to be phase compensated to capture SYSREF. Therefore, you can generate both the link clock and frame clock using direct mode in the PLL Intel® FPGA IP core. If F = 4, where link clock is the same as the frame clock, you can use the parallel clock output from the transceiver (txphy_clk or rxphy_clk signal) except when the PCS option is in PMA Direct mode.