4.7.2. Transmitter Registers
Bit | Name | Description | Attribute | Reset |
---|---|---|---|---|
31:3 | Reserved | Reserved | R | 0x0 |
2 | rl | Physical lane control reserve register | RW | 0x0 |
1 | csr_bit reversal | Bit reversal for LSB/MSB first serialization. This is a compile-time option which needs to be set before IP generation.
Note: JESD204B converter device may support either MSB-first serialization or LSB-first serialization.
You must set both csr_byte_reversal and csr_bit_reversal bits to 1 when generating the IP. When csr_bit_reversal = 1, the word aligner reverses the TX parallel data bits before transmitting it to the PMA for serialization. For example; in 20-bit mode; D[19:0] is rewired to D[0:19] and in 40-bit mode; D[39:0] is rewired to D[0:39]. |
R | Compile-time specific |
0 | csr_byte reversal | Byte reversal for LSB/MSB first serialization. This is a compile-time option which needs to be set before IP generation.
Note: JESD204B converter device may support either MSB-first serialization or LSB-first serialization.
When csr_byte_reversal = 1, the byte order is reversed before transmitting data. |
R | Compile-time specific |
Bit | Name | Description | Attribute | Reset |
---|---|---|---|---|
31:10 | Reserved | Reserved | R | 0x0 |
9:2 | rl0 | Physical lane control reserve register | RW | 0x0 |
1 | csr_lane0_powerdown | Power down control for lane 0. This register routes out of the IP as csr_lane_powerdown[0]. The transport layer (TL) uses this signal to indicate the fall back of the lanes (L) for run-time LMF support. To save power, route this signal to the Transceiver Reset Controller block as an assert mask for rx_digitalreset and rx_analogreset to power down the lane.
Note: This status bit is not applicable for Intel Agilex® 7 and Intel® Stratix® 10 E-tile devices.
|
RW | 0x0 |
0 | csr_lane0_polarity | Set 1 to inverse lane 0 polarity. When set, the TX interface inverts the polarity of the TX data. You can use this bit to correct the polarity of differential pairs if the transmission circuitry or board layout mistakenly swaps the positive and negative signals. |
RW | 0x0 |
Bit | Name | Description | Attribute | Reset |
---|---|---|---|---|
31:10 | Reserved | Reserved | R | 0x0 |
9:2 | rl1 | Physical lane control reserve register | RW | 0x0 |
1 | csr_lane1_powerdown | Power down control for lane 1. This register routes out of the IP as csr_lane_powerdown[1]. The transport layer (TL) uses this signal to indicate the fall back of the lanes (L) for run-time LMF support. To save power, route this signal to the Transceiver Reset Controller block as an assert mask for rx_digitalreset and rx_analogreset to power down the lane.
Note: This status bit is not applicable for Intel Agilex® 7 and Intel® Stratix® 10 E-tile devices.
|
RW | 0x0 |
0 | csr_lane1_polarity | Set 1 to inverse lane 1 polarity. When set, the TX interface inverts the polarity of the TX data. You can use this bit to correct the polarity of differential pairs if the transmission circuitry or board layout mistakenly swaps the positive and negative signals. |
RW | 0x0 |
Bit | Name | Description | Attribute | Reset |
---|---|---|---|---|
31:10 | Reserved | Reserved | R | 0x0 |
9:2 | rl2 | Physical lane control reserve register | RW | 0x0 |
1 | csr_lane2_powerdown | Power down control for lane 2. This register routes out of the IP as csr_lane_powerdown[2]. The transport layer (TL) uses this signal to indicate the fall back of the lanes (L) for run-time LMF support. To save power, route this signal to the Transceiver Reset Controller block as an assert mask for rx_digitalreset and rx_analogreset to power down the lane.
Note: This status bit is not applicable for Intel Agilex® 7 and Intel® Stratix® 10 E-tile devices.
|
RW | 0x0 |
0 | csr_lane2_polarity | Set 1 to inverse lane 2 polarity. When set, the TX interface inverts the polarity of the TX data. You can use this bit to correct the polarity of differential pairs if the transmission circuitry or board layout mistakenly swaps the positive and negative signals. |
RW | 0x0 |
Bit | Name | Description | Attribute | Reset |
---|---|---|---|---|
31:10 | Reserved | Reserved | R | 0x0 |
9:2 | rl3 | Physical lane control reserve register | RW | 0x0 |
1 | csr_lane3_powerdown | Power down control for lane 3. This register routes out of the IP as csr_lane_powerdown[3]. The transport layer (TL) uses this signal to indicate the fall back of the lanes (L) for run-time LMF support. To save power, route this signal to the Transceiver Reset Controller block as an assert mask for rx_digitalreset and rx_analogreset to power down the lane.
Note: This status bit is not applicable for Intel Agilex® 7 and Intel® Stratix® 10 E-tile devices.
|
RW | 0x0 |
0 | csr_lane3_polarity | Set 1 to inverse lane 3 polarity. When set, the TX interface inverts the polarity of the TX data. You can use this bit to correct the polarity of differential pairs if the transmission circuitry or board layout mistakenly swaps the positive and negative signals. |
RW | 0x0 |
Bit | Name | Description | Attribute | Reset |
---|---|---|---|---|
31:10 | Reserved | Reserved | R | 0x0 |
9:2 | rl4 | Physical lane control reserve register | RW | 0x0 |
1 | csr_lane4_powerdown | Power down control for lane 4. This register routes out of the IP as csr_lane_powerdown[4]. The transport layer (TL) uses this signal to indicate the fall back of the lanes (L) for run-time LMF support. To save power, route this signal to the Transceiver Reset Controller block as an assert mask for rx_digitalreset and rx_analogreset to power down the lane.
Note: This status bit is not applicable for Intel Agilex® 7 and Intel® Stratix® 10 E-tile devices.
|
RW | 0x0 |
0 | csr_lane4_polarity | Set 1 to inverse lane 4 polarity. When set, the TX interface inverts the polarity of the TX data. You can use this bit to correct the polarity of differential pairs if the transmission circuitry or board layout mistakenly swaps the positive and negative signals. |
RW | 0x0 |
Bit | Name | Description | Attribute | Reset |
---|---|---|---|---|
31:10 | Reserved | Reserved | R | 0x0 |
9:2 | rl5 | Physical lane control reserve register | RW | 0x0 |
1 | csr_lane5_powerdown | Power down control for lane 5. This register routes out of the IP as csr_lane_powerdown[5]. The transport layer (TL) uses this signal to indicate the fall back of the lanes (L) for run-time LMF support. To save power, route this signal to the Transceiver Reset Controller block as an assert mask for rx_digitalreset and rx_analogreset to power down the lane.
Note: This status bit is not applicable for Intel Agilex® 7 and Intel® Stratix® 10 E-tile devices.
|
RW | 0x0 |
0 | csr_lane5_polarity | Set 1 to inverse lane 5 polarity. When set, the TX interface inverts the polarity of the TX data. You can use this bit to correct the polarity of differential pairs if the transmission circuitry or board layout mistakenly swaps the positive and negative signals. |
RW | 0x0 |
Bit | Name | Description | Attribute | Reset |
---|---|---|---|---|
31:10 | Reserved | Reserved | R | 0x0 |
9:2 | rl6 | Physical lane control reserve register | RW | 0x0 |
1 | csr_lane6_powerdown | Power down control for lane 6. This register routes out of the IP as csr_lane_powerdown[6]. The transport layer (TL) uses this signal to indicate the fall back of the lanes (L) for run-time LMF support. To save power, route this signal to the Transceiver Reset Controller block as an assert mask for rx_digitalreset and rx_analogreset to power down the lane.
Note: This status bit is not applicable for Intel Agilex® 7 and Intel® Stratix® 10 E-tile devices.
|
RW | 0x0 |
0 | csr_lane6_polarity | Set 1 to inverse lane 6 polarity. When set, the TX interface inverts the polarity of the TX data. You can use this bit to correct the polarity of differential pairs if the transmission circuitry or board layout mistakenly swaps the positive and negative signals. |
RW | 0x0 |
Bit | Name | Description | Attribute | Reset |
---|---|---|---|---|
31:10 | Reserved | Reserved | R | 0x0 |
9:2 | rl7 | Physical lane control reserve register | RW | 0x0 |
1 | csr_lane7_powerdown | Power down control for lane 7. This register routes out of the IP as csr_lane_powerdown[7]. The transport layer (TL) uses this signal to indicate the fall back of the lanes (L) for run-time LMF support. To save power, route this signal to the Transceiver Reset Controller block as an assert mask for rx_digitalreset and rx_analogreset to power down the lane.
Note: This status bit is not applicable for Intel Agilex® 7 and Intel® Stratix® 10 E-tile devices.
|
RW | 0x0 |
0 | csr_lane7_polarity | Set 1 to inverse lane 7 polarity. When set, the TX interface inverts the polarity of the TX data. You can use this bit to correct the polarity of differential pairs if the transmission circuitry or board layout mistakenly swaps the positive and negative signals. |
RW | 0x0 |
Bit | Name | Description | Attribute | Reset |
---|---|---|---|---|
31:17 | Reserved | Reserved | R | 0x0 |
16 | rd5 | DLL control reserve register 5 | RW | 0x0 |
15 | rd4 | DLL control reserve register 4 | RW | 0x0 |
14 | rd3 | DLL control reserve register 3 | RW | 0x0 |
13 | rd2 | DLL control reserve register 2 | RW | 0x0 |
12 | rd1 | DLL control reserve register 1 | RW | 0x0 |
11 | csr_reinit_rxsyncn_rise | Control CGS state exit behavior during link reinitialization through syncn_sysref_ctrl (0x54) csr_link_reinit.
|
RW | 0x0 |
10 | test_ilas_loop | Write 1 to this register will force the state machine to stay in Initial Lane Alignment Sequence (ILAS) state indefinitely after entry. ILAS Configuration will be transmitted during the second ILAS multiframe. The rest of the multiframe will have the start-of-multiframe character (/R/) followed by dummy data and end-of-multiframe (/A/). There are 2 modes of entry per JESD204B Specification, chapter 5.3.3.8.2:
|
RW | 0x0 |
9 | csr_char_repl_disable | Disable character replacement for debug purposes. When this bit is set, end-of-frame (/F/) and end-of-multiframe (/A/) character replacement will be disabled.
|
RW | 0x0 |
8:1 | csr_ilas_multiframe | The counter is binary value minus 1. ILAS required by subclass 1 and 2 consists of exactly 4 multiframes. However, configurations with multiple subclass 0 DAC devices may require additional multiframes to achieve lane alignment. Therefore, the length of ILAS shall be programmable from 4 up to 256 multiframes. When illegal values like 0/1/2 is set, the IP will still run as 4 multiframes.
Note: This counter value takes effect regardless of subclass setting. Do not to change this register for Subclass 1 and Subclass 2.
|
RW | 0x0 |
0 | csr_lane_sync_en | Lane synchronization enable is required multilane alignment for a JESD204B link.
Note: For device that is classified as NMCDA-SL, you can disable lane synchronization. Set this bit to 1 for all other devices.
|
RW | 0x0 |
Bit | Name | Description | Attribute | Reset |
---|---|---|---|---|
31:21 | Reserved | Reserved | R | 0x0 |
20 | csr_cgs_bypass_sysref | This bit applies to Subclass 1 only. Enabling DLL states transition from Code Group Synchronization (CGS) to Initial Lane Alignment Sequence (ILAS) to bypass SYSREF single detect sampling. By default, the JESD204B IP will remain in CGS state until SYSREF is sampled. Once csr_sysref_singledet is cleared, then only the DLL state can transition from CGS to ILAS on the next LMFC tick. Write 1 to this register to allow the IP to exit out of CGS state without ensuring that at least one rising edge of SYSREF was sampled.
Note: This is a debug mode, where you can bypass SYSREF sampling if only a quick link up is required. Setting this bit to 1 may cause race condition between SYSREF sampling and CGS exit.
|
RW | 0x0 |
19:12 | csr_lmfc_offset | The Local Multiframe Clock (LMFC) offset is a binary value minus 1. Upon the detection of the rising edge of SYSREF in continuous mode or single detect mode, the LMFC counter will be reset to the value set in csr_lmfc_offset. The LMFC counter operates in link clock domain, therefore the legal value for the counter is from 0 to ((FxK/4)-1. If you set an out-of-range value, the LMFC offset internally resets to 0.
Note: By default, the rising edge of SYSREF will reset the LMFC counter to 0. However, if the system design has large phase offset between the SYSREF sampled by the converter device and the FPGA, you can virtually shift the SYSREF edges by changing the LMFC offset reset value using this register.
|
RW | 0x0 |
11:7 | Reserved | Reserved | R | 0x0 |
6 | rs4 | SYNCN and SYSREF control reserve register 4 | RW | 0x0 |
5 | rs3 | SYNCN and SYSREF control reserve register 3 | RW | 0x0 |
4 | rs2 | SYNCN and SYSREF control reserve register 2 | RW | 0x0 |
3 | rs1 | SYNCN and SYSREF control reserve register 1 | RW | 0x0 |
2 | csr_sysref_singledet | This register enables LMFC realignment with a single sample of rising edge of SYSREF. The bit is auto-cleared by hardware once SYSREF is sampled. If you require SYSREF to be sampled again (due to link reset or reinitialization), you must set this bit again. This register also has another critical function. The JESD204B IP will never will never exit out of CGS unless at least a SYSREF edge is sampled. This is to prevent race condition between SYSREF being sampled and the exit of CGS to ILAS. If CGS transition to ILAS before the common SYSREF is sampled for both the IP and converter device, this would cause undeterministic latency as the transmitted ILAS is based on the free running LMFC counter coming out of reset.
Note: Intel recommends that you use csr_sysref_singledet with csr_sysref_alwayson even if you want to do SYSREF continuous detection mode. This is because this register is able to indicate whether SYSREF was ever sampled. This register also prevents race condition as mentioned above. Using only SYSREF single detect mode will not be able to detect incorrect SYSREF period.
|
RW | 0x1 |
1 | csr_sysref_alwayson | This register enables LMFC realignment at every rising edge of SYSREF. LMFC counter is reset when every SYSREF transition from 0 to 1 is detected.
Note: When this bit is set, the SYSREF period will be checked to ensure it never violates internal local multiframe period and this period can only be n-integer multiplied of ((FxK)/4. If the SYSREF period is different from the local multiframe period, tx_err (0x60) csr_sysref_lmfc_err will be asserted and an interrupt will be triggered.
If you want to change SYSREF period, this bit should be set to 0 first. After SYSREF clock has stabilized, this bit is set to 1 to sample the rising edges of the new SYSREF. |
RW | 0x0 |
0 | csr_link_reinit | The JESD204B IP will reinitialize the link to enter Code Group Synchronization by transmitting /K28.5. The software will need to check that SYNC_N tx_status0 (0x80) csr_dev_syncn is 1 before setting this register. This bit automatically clears once link reinitialization is entered by hardware.
|
RW | 0x0 |
Bit | Name | Description | Attribute | Reset |
---|---|---|---|---|
31:9 | Reserved | Reserved | R | 0x0 |
8 | re4 | TX error reserve status 4 | RW | 0x0 |
7 | csr_pcfifo_empty_err | Detected 1 or more lanes of Phase Compensation FIFO is empty unexpectedly when the JESD204B link is running.
Note: This status bit is not applicable for Intel Agilex® 7 and Intel® Stratix® 10 devices.
Note: You MUST reset the JESD204B link if this bit is triggered. The transceiver channel, and the IP link reset must be applied.
|
RW1C | 0x0 |
6 | csr_pcfifo_full_err | Detected 1 or more lanes of Phase Compensation FIFO is full unexpectedly when the JESD204B link is running.
Note: This status bit is not applicable for Intel Agilex® 7 and Intel® Stratix® 10 devices.
Note: You MUST reset the JESD204B link if this bit is triggered. The transceiver channel, and the IP link reset must be applied.
|
RW1C | 0x0 |
5 | csr_pll_locked_err | Detected 1 or more lanes of PLL locked loose lock when the JESD204B link is running.
Note: This status bit is not applicable for Intel Agilex® 7 and Intel® Stratix® 10 E-tile devices.
|
RW1C | 0x0 |
4 | csr_syncn_reinit_req | Receiver has requested reinitialization by asserting SYNC_N low for more than 5 frames and 9 octets.
Note: Upon the detection of SYNC_N link reinitialization request from the receiver, the JESD204B IP enters Code Group Synchronization (CGS) and transmits continuous /K28.5/. If you want to regenerate and sample SYSREF, enabling this interrupt notifies the software that the receiver has requested for link reinitialization.
|
RW1C | 0x0 |
3 | csr_frame_data_invalid_err | This error bit is applicable only if you use the Intel FPGA transport layer in your design. This error bit will be asserted if the upstream component deasserts the jesd204_tx_data_valid signal at the Intel FPGA transport layer AV-ST bus. The transport layer expects the upstream device in the system to always send the valid data with zero latency when jesd204_tx_data_ready is asserted by the transport layer.
Note: If this error detection is not required, you can tie off the jesd204_tx_frame_error signal to 0.
|
RW1C | 0x0 |
2 | csr_dll_data_invalid_err | This error bit will be asserted if the TX detects data invalid on the AV-ST bus when data is requested. By design, the JESD204B TX core expects the upstream device (JESD204B transport layer) to always send the valid data with zero latency when jesd204_tx_data_ready is asserted.
Note: If this error detection is not required, you can tie off the jesd204_tx_link_valid signal to 1.
|
RW1C | 0x0 |
1 | csr_sysref_lmfc_err | When syncn_sysref_ctrl (0x54) csr_sysref_alwayson is set to 1, the LMFC counter checks whether the SYSREF period matches the LMFC counter where it is n-integer multiplier of the (FxK/4). If SYSREF period does not match the LMFC period, this bit will be asserted. |
RW1C | 0x0 |
0 | csr_syncn_err | The JESD204B receiver indicates error through the SYNC_N signal. |
RW1C | 0x0 |
Bit | Name | Description | Attribute | Reset |
---|---|---|---|---|
31:9 | Reserved | Reserved | R | 0x0 |
8 | re4_en | TX error enable reserve 4 | RW | 0x1 |
7 | csr_pcfifo_empty_err_en | Enable interrupt for Phase Compensation FIFO empty error | RW | 0x1 |
6 | csr_pcfifo_full_err_en | Enable interrupt for Phase Compensation FIFO full error | RW | 0x1 |
5 | csr_pll_locked_err_en | Enable interrupt for PLL loose lock error.
Note: This status bit is not applicable for Intel Agilex® 7 and Intel® Stratix® 10 E-tile devices.
|
RW | 0x1 |
4 | csr_syncn_reinit_req_en | Enable interrupt for SYNCN reinit request. | RW | 0x1 |
3 | csr_frame_data_invalid_err_en | Enable interrupt for transport layer data invalid error type. | RW | 0x0 |
2 | csr_dll_data_invalid_err_en | Enable interrupt for DLL data invalid error type. | RW | 0x0 |
1 | csr_sysref_lmfc_err_en | Enable interrupt for SYSREF LMFC error type. | RW | 0x0 |
0 | csr_syncn_err_en | Enable interrupt for SYNC_N error type. | RW | 0x1 |
Bit | Name | Description | Attribute | Reset |
---|---|---|---|---|
31:21 | Reserved | Reserved | R | 0x0 |
20:13 | csr_dbg_adjcnt | Number of adjustment resolution steps of DAC LMFC in device link clock resolution. Applies to Subclass 2 only.
Note: For Subclass 2 operations, the JESD204B IP calculates the phase of the SYNC_N deassertion from the receiver with respect to internal LMFC counter. Interrupt will be triggered with either tx_err (0x60) csr_syncn_err or csr_syncn_reinit_req set. This register along with csr_dbg_adjdir and csr_dbg_phadj latch the phase offset, direction and resolution based on phase detection using link clock. Hysteresis and device clock ratio calculation should be done in the software.
|
R | 0x0 |
12 | csr_dbg_adjdir | Adjustment direction of DAC LMFC to the nearest LMFC tick. Applies to Subclass 2 only.
Note: For Subclass 2 operations, the JESD204B IP calculates the phase of the SYNC_N deassertion from the receiver with respect to internal LMFC counter. Interrupt will be triggered with either tx_err (0x60) csr_syncn_err or csr_syncn_reinit_req set. This register along with csr_dbg_phadj and csr_dbg_adjcnt latch the phase offset, direction and resolution based on phase detection using link clock. Hysteresis and device clock ratio calculation should be done in the software.
|
0x0 | |
11 | csr_dbg_phadj | SYNC_N deassertion is not-in-phase with the internal LMFC counter. Applies to Subclass 2 only.
Note: For Subclass 2 operations, the JESD204B IP calculates the phase of the SYNC_N deassertion from the receiver with respect to internal LMFC counter. Interrupt will be triggered with either tx_err (0x60) csr_syncn_err or csr_syncn_reinit_req set. This register along with csr_dbg_adjdir and csr_dbg_adjcnt latch the phase offset, direction and resolution based on phase detection using link clock. Hysteresis and device clock ratio calculation should be done in the software.
|
0x0 | |
10:3 | csr_ilas_cnt | This register is a binary minus 1 value. The counter value reflects on which number of ILAS multiframe the DLL state machine is in. | R | 0x0 |
2:1 | csr_dll_state | Current state of data link layer (DLL).
|
R | 0x0 |
0 | csr_dev_syncn | Internal SYNC_N value.
|
R | 0x0 |
Bit | Name | Description | Attribute | Reset |
---|---|---|---|---|
31:24 | Reserved | Reserved | R | 0x0 |
23 | csr_lane7_tx_pcfifo_empty | TX phase compensation FIFO status empty flag for lane 7 | R | 0x0 |
22 | csr_lane6_tx_pcfifo_empty | TX phase compensation FIFO status empty flag for lane 6 | R | 0x0 |
21 | csr_lane5_tx_pcfifo_empty | TX phase compensation FIFO status empty flag for lane 5 | R | 0x0 |
20 | csr_lane4_tx_pcfifo_empty | TX phase compensation FIFO status empty flag for lane 4 | R | 0x0 |
19 | csr_lane3_tx_pcfifo_empty | TX phase compensation FIFO status empty flag for lane 3 | R | 0x0 |
18 | csr_lane2_tx_pcfifo_empty | TX phase compensation FIFO status empty flag for lane 2 | R | 0x0 |
17 | csr_lane1_tx_pcfifo_empty | TX phase compensation FIFO status empty flag for lane 1 | R | 0x0 |
16 | csr_lane0_tx_pcfifo_empty | TX phase compensation FIFO status empty flag for lane 0 | R | 0x0 |
15:8 | Reserved | Reserved | R | 0x0 |
7 | csr_lane7_tx_pcfifo_full | TX phase compensation FIFO status full flag for lane 7 | R | 0x0 |
6 | csr_lane6_tx_pcfifo_full | TX phase compensation FIFO status full flag for lane 6 | R | 0x0 |
5 | csr_lane5_tx_pcfifo_full | TX phase compensation FIFO status full flag for lane 5 | R | 0x0 |
4 | csr_lane4_tx_pcfifo_full | TX phase compensation FIFO status full flag for lane 4 | R | 0x0 |
3 | csr_lane3_tx_pcfifo_full | TX phase compensation FIFO status full flag for lane 3 | R | 0x0 |
2 | csr_lane2_tx_pcfifo_full | TX phase compensation FIFO status full flag for lane 2 | R | 0x0 |
1 | csr_lane1_tx_pcfifo_full | TX phase compensation FIFO status full flag for lane 1 | R | 0x0 |
0 | csr_lane0_tx_pcfifo_full | TX phase compensation FIFO status full flag for lane 0 | R | 0x0 |
Bit | Name | Description | Attribute | Reset |
---|---|---|---|---|
31:24 | Reserved | Reserved | R | 0x0 |
23 | csr_lane7_pll_locked | PLL status for lane 7, indicates PLL is locked. For Intel Agilex® 7 and Intel® Stratix® 10 E-tile devices, tie this register to 1’b1. |
R | 0x0 |
22 | csr_lane6_pll_locked | PLL status for lane 6, indicates PLL is locked. For Intel Agilex® 7 and Intel® Stratix® 10 E-tile devices, tie this register to 1’b1. |
R | 0x0 |
21 | csr_lane5_pll_locked | PLL status for lane 5, indicates PLL is locked. For Intel Agilex® 7 and Intel® Stratix® 10 E-tile devices, tie this register to 1’b1. |
R | 0x0 |
20 | csr_lane4_pll_locked | PLL status for lane 4, indicates PLL is locked. For Intel Agilex® 7 and Intel® Stratix® 10 E-tile devices, tie this register to 1’b1. |
R | 0x0 |
19 | csr_lane3_pll_locked | PLL status for lane 3, indicates PLL is locked. For Intel Agilex® 7 and Intel® Stratix® 10 E-tile devices, tie this register to 1’b1. |
R | 0x0 |
18 | csr_lane2_pll_locked | PLL status for lane 2, indicates PLL is locked. For Intel Agilex® 7 and Intel® Stratix® 10 E-tile devices, tie this register to 1’b1. |
R | 0x0 |
17 | csr_lane1_pll_locked | PLL status for lane 1, indicates PLL is locked. For Intel Agilex® 7 and Intel® Stratix® 10 E-tile devices, tie this register to 1’b1. |
R | 0x0 |
16 | csr_lane0_pll_locked | PLL status for lane 0, indicates PLL is locked. For bonded mode, the transceiver generates only one PLL locked signal. The single bit will be routed to lane 0 of PLL locked status. All other lanes will be tied off to 0. For non-bonded mode, PLL locked status will be per channel. The status will be routed to the respective PLL locked status per channel. For Intel Agilex® 7 and Intel® Stratix® 10 E-tile devices, tie this register to 1’b1. |
R | 0x0 |
15:8 | Reserved | Reserved | R | 0x0 |
7 | csr_lane7_tx_cal_busy | Reconfig status for lane 7, indicates TX calibration is in progress.
Note: This status bit is not applicable for Intel Agilex® 7 and Intel® Stratix® 10 E-tile devices.
|
R | 0x0 |
6 | csr_lane6_tx_cal_busy | Reconfig status for lane 6, indicates TX calibration is in progress.
Note: This status bit is not applicable for Intel Agilex® 7 and Intel® Stratix® 10 E-tile devices.
|
R | 0x0 |
5 | csr_lane5_tx_cal_busy | Reconfig status for lane 5, indicates TX calibration is in progress.
Note: This status bit is not applicable for Intel Agilex® 7 and Intel® Stratix® 10 E-tile devices.
|
R | 0x0 |
4 | csr_lane4_tx_cal_busy | Reconfig status for lane 4, indicates TX calibration is in progress.
Note: This status bit is not applicable for Intel Agilex® 7 and Intel® Stratix® 10 E-tile devices.
|
R | 0x0 |
3 | csr_lane3_tx_cal_busy | Reconfig status for lane 3, indicates TX calibration is in progress.
Note: This status bit is not applicable for Intel Agilex® 7 and Intel® Stratix® 10 E-tile devices.
|
R | 0x0 |
2 | csr_lane2_tx_cal_busy | Reconfig status for lane 2, indicates TX calibration is in progress.
Note: This status bit is not applicable for Intel Agilex® 7 and Intel® Stratix® 10 E-tile devices.
|
R | 0x0 |
1 | csr_lane1_tx_cal_busy | Reconfig status for lane 1, indicates TX calibration is in progress.
Note: This status bit is not applicable for Intel Agilex® 7 and Intel® Stratix® 10 E-tile devices.
|
R | 0x0 |
0 | csr_lane0_tx_cal_busy | Reconfig status for lane 0, indicates TX calibration is in progress.
Note: This status bit is not applicable for Intel Agilex® 7 and Intel® Stratix® 10 E-tile devices.
. |
R | 0x0 |
Bit | Name | Description | Attribute | Reset |
---|---|---|---|---|
31:0 | rs32 | TX status reserve. | R | 0x0 |
Bit | Name | Description | Attribute | Reset |
---|---|---|---|---|
31:24 | csr_m | Link M. Number of converters per device (binary value minus 1).
Note: Run-time reconfiguration is disabled for Intel Agilex® 7 and Intel® Stratix® 10 devices.
|
|
Reset to parameter value per IP generation. |
23:21 | Reserved | Reserved | R | 0x0 |
20:16 | csr_k | Link K. Number of frames per multiframe (binary value minus 1). A multiframe is defined as a group of K successive frames where K is between 1 and 32 and such that the number of octets per multiframe is between 17 and 1024. The IP requires that FxK must be divisible by 4.
Note: Run-time reconfiguration is disabled for Intel Agilex® 7 and Intel® Stratix® 10 devices.
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Reset to parameter value per IP generation. |
15:8 | csr_f | Link F. Number of octets per frame (binary value minus 1).
Note: Run-time reconfiguration is disabled for Intel Agilex® 7 and Intel® Stratix® 10 devices.
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Reset to parameter value per IP generation. |
7 | csr_scr_en | Enable or disable descrambler.
Note: Run-time reconfiguration is disabled for Intel Agilex® 7 and Intel® Stratix® 10 devices.
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Reset to parameter value per IP generation. |
6:5 | Reserved | Reserved | R | 0x0 |
4:0 | csr_l | Link L. Number of lanes per converter (binary value minus 1).
Note: Run-time reconfiguration is disabled for Intel Agilex® 7 and Intel® Stratix® 10 devices.
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Reset to parameter value per IP generation. |
Bit | Name | Description | Attribute | Reset |
---|---|---|---|---|
31 | csr_hd | Link HD. High density format.
Note: Run-time reconfiguration is disabled for Intel Agilex® 7 and Intel® Stratix® 10 devices.
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Reset to parameter value per IP generation. |
30:29 | Reserved | Reserved | R | 0x0 |
28:24 | csr_cf | Link CF.
Number of control words per frame clock period per link
Note: Run-time reconfiguration is disabled for Intel Agilex® 7 and Intel® Stratix® 10 devices.
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Reset to parameter value per IP generation. |
23:21 | csr_jesdv | JESD204x version.
Note: Run-time reconfiguration is disabled for Intel® Stratix® 10 devices.
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0x1 |
20:16 | csr_s | Link S. Number of samples per converter per frame cycle (binary value minus 1).
Note: Run-time reconfiguration is disabled for Intel® Stratix® 10 devices.
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Reset to parameter value per IP generation. |
15:13 | csr_subclassv | Device subclass version
Note: Run-time reconfiguration is disabled for Intel Agilex® 7 and Intel® Stratix® 10 devices.
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Reset to parameter value per IP generation. |
12.8 | csr_np | Link NP. Total number of bits per sample (binary value minus 1).
Note: Run-time reconfiguration is disabled for Intel Agilex® 7 and Intel® Stratix® 10 devices.
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Reset to parameter value per IP generation. |
7:6 | csr_cs | Link CS. Number of control bits per sample.
Note: Run-time reconfiguration is disabled for Intel Agilex® 7 and Intel® Stratix® 10 devices.
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Reset to parameter value per IP generation. |
5 | Reserved | Reserved | R | 0x0 |
4:0 | csr_n | Link N. Converter resolution (binary value minus 1).
Note: Run-time reconfiguration is disabled for Intel Agilex® 7 and Intel® Stratix® 10 devices.
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Reset to parameter value per IP generation. |
Bit | Name | Description | Attribute | Reset |
---|---|---|---|---|
31 | csr_phadj | Phase adjustment request of DAC LMFC. The register is auto-cleared by the hardware after sending ILAS 2nd multiframe. Applies to Subclass 2 only. |
RW | Reset to parameter value per IP generation. |
30 | csr_adjdir | Adjustment direction of DAC LMFC. The register is auto-cleared by the hardware after sending ILAS 2nd multiframe. Applies to Subclass 2 only.
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RW | Reset to parameter value per IP generation. |
29:20 | Reserved | Reserved | R | 0x0 |
19:16 | csr_f | Number of adjustment resolution steps of DAC LMFC. The register is auto-cleared by the hardware after sending ILAS 2nd multiframe. Applies to Subclass 2 only. |
RW | Reset to parameter value per IP generation. |
15:8 | csr_rsvd2 | ILAS reserved 2 bytes. | RW | 0x00 |
7:0 | csr_rsvd1 | ILAS reserved 1 bytes. | RW | 0x00 |
Bit | Name | Description | Attribute | Reset |
---|---|---|---|---|
31:29 | Reserved | Reserved | R | 0x0 |
28:24 | csr_lid_l3 | Lane Identification for lane 3 transmitted during ILAS. |
RW | Reset to parameter value per IP generation. |
23:21 | Reserved | Reserved | R | 0x0 |
20:16 | csr_lid_l2 | Lane Identification for lane 2 transmitted during ILAS. |
RW | Reset to parameter value per IP generation. |
15:13 | Reserved | Reserved | R | 0x0 |
12:8 | csr_lid_l1 | Lane Identification for lane 1 transmitted during ILAS. |
RW | Reset to parameter value per IP generation. |
7:5 | Reserved | Reserved | R | 0x0 |
4:0 | csr_lid_l0 | Lane Identification for lane 0 transmitted during ILAS. |
RW | Reset to parameter value per IP generation. |
Bit | Name | Description | Attribute | Reset |
---|---|---|---|---|
31:29 | Reserved | Reserved | R | 0x0 |
28:24 | csr_lid_l7 | Lane Identification for lane 7 transmitted during ILAS. |
RW | Reset to parameter value per IP generation. |
23:21 | Reserved | Reserved | R | 0x0 |
20:16 | csr_lid_l6 | Lane Identification for lane 6 transmitted during ILAS. |
RW | Reset to parameter value per IP generation. |
15:13 | Reserved | Reserved | R | 0x0 |
12:8 | csr_lid_l5 | Lane Identification for lane 5 transmitted during ILAS. |
RW | Reset to parameter value per IP generation. |
7:5 | Reserved | Reserved | R | 0x0 |
4:0 | csr_lid_l4 | Lane Identification for lane 4 transmitted during ILAS. |
RW | Reset to parameter value per IP generation. |
Bit | Name | Description | Attribute | Reset |
---|---|---|---|---|
31:24 | csr_fchk_l3 | ILAS checksum lane 3. Checksum is the modulo 256 of parameters listed ILAS configuration data. |
RW | Reset to parameter value per IP generation. |
23:16 | csr_fchk_l2 | ILAS checksum lane 2. Checksum is the modulo 256 of parameters listed ILAS configuration data. |
RW | Reset to parameter value per IP generation. |
15:8 | csr_fchk_l1 | ILAS checksum lane 1. Checksum is the modulo 256 of parameters listed ILAS configuration data. |
RW | Reset to parameter value per IP generation. |
7:0 | csr_fchk_l0 | ILAS checksum lane 0. Checksum is the modulo 256 of parameters listed ILAS configuration data. |
RW | Reset to parameter value per IP generation. |
Bit | Name | Description | Attribute | Reset |
---|---|---|---|---|
31:10 | csr_fchk_l7 | ILAS checksum lane 7. Checksum is the modulo 256 of parameters listed ILAS configuration data. |
RW | Reset to parameter value per IP generation. |
23:16 | csr_fchk_l6 | ILAS checksum lane 6. Checksum is the modulo 256 of parameters listed ILAS configuration data. |
RW | Reset to parameter value per IP generation. |
15:8 | csr_fchk_l5 | ILAS checksum lane 5. Checksum is the modulo 256 of parameters listed ILAS configuration data. |
RW | Reset to parameter value per IP generation. |
7:0 | csr_fchk_l4 | ILAS checksum lane 4. Checksum is the modulo 256 of parameters listed ILAS configuration data. |
RW | Reset to parameter value per IP generation. |
Bit | Name | Description | Attribute | Reset |
---|---|---|---|---|
31:10 | Reserved | Reserved | R | 0x0 |
9:2 | csr_fxk_h | Upper bits of FxK[8:2]. This is a binary value minus 1. Link F multiply with Link K must be divisible by 4.
Note: The IP runs on 32-bit data width boundary per channel, so you must always ensure that FxK must be divisible by 4.
Note: Run-time reconfiguration is disabled for Intel Agilex® 7 and Intel® Stratix® 10 devices.
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Reset to parameter value per IP generation. |
1:0 | csr_fxk_l | Lower bits of FxK[1:0]. This is a binary value minus 1. Link F multiply with Link K must be divisible by 4.
Note: The IP runs on 32-bit data width boundary per channel, so you must always ensure that FxK must be divisible by 4. FxK (in binary value minus 1) always results to a value of 2'b11in the lower 2 bits.
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R | 0x3 |
Bit | Name | Description | Attribute | Reset |
---|---|---|---|---|
31:4 | Reserved | Reserved | R | 0x0 |
3:0 | csr_tx_testmode | b0xxx is reserved for the JESD204B IP and 'b1xxx is reserved for external components out of the JESD204B IP. JESD204B IP test mode:
JESD204B IP reference design test mode:
|
RW | 0x0 |
Bit | Name | Description | Attribute | Reset |
---|---|---|---|---|
31:16 | test_pattern1 | User test pattern 1. | RW | 0x0000 |
15:0 | test_pattern0 | User test pattern 0. | RW | 0x0000 |
Bit | Name | Description | Attribute | Reset |
---|---|---|---|---|
31:16 | test_pattern3 | User test pattern 3. | RW | 0x0000 |
15:0 | test_pattern2 | User test pattern 2. | RW | 0x0000 |
Bit | Name | Description | Attribute | Reset |
---|---|---|---|---|
31:16 | test_pattern5 | User test pattern 5. | RW | 0x0000 |
15:0 | test_pattern4 | User test pattern 4. | RW | 0x0000 |
Bit | Name | Description | Attribute | Reset |
---|---|---|---|---|
31:16 | test_pattern7 | User test pattern 7. | RW | 0x0000 |
15:0 | test_pattern6 | User test pattern 6. | RW | 0x0000 |