JESD204B Intel® FPGA IP User Guide

ID 683442
Date 7/20/2023
Document Table of Contents
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6.5. Signal Polarity and FPGA Pin Assignment

Verify that the transceiver channel pin assignments—SYNC_N and SYSREF (for Subclass 1 only)—device clock, and SPI interface are correct. Also verify the signal polarity of the differential pairs like SYNC_N and transceiver channels are correct.

Check these items:

  • Review the schematic and board layout file to determine the polarity of the physical pin connection.
  • Use assignment editor and pin planner to check the pin assignment and I/O standard for each pin.
  • Use RTL viewer in the Intel® Quartus® Prime software to verify that the top level port are connected to the lower level module that you instantiate.