JESD204B Intel® FPGA IP User Guide

ID 683442
Date 7/20/2023
Document Table of Contents

5.1. SYSREF Guidelines

  • The designer must decide how the device clock and SYSREF signal is created and distributed throughout the system. In the JESD204B subclass 1 system level application, you must generate SYSREF from the same source as the device clock. Sample subclass 1 system level application implementation can be found on Intel JESD204B IP Interoperability reports.
  • SYSREF Frequency = Local Multiframe Clock / n; (n = integer; 1, 2, …). Refer to Clock Correlation.
  • Ensure incoming SYSREF signal is constrained so that the setup relationship between SYSREF and the device clock is established. Refer to Constraining Incoming SYSREF Signal.
    • Set the timing constraint for the SYSREF signal in the user .sdc file. When the setup time is met, the SYSREF signal detection by the IP and the number of link clock cycles of SYSREF signal that arrives at the FPGA pin to the LMFC counter resets are deterministic.
    • To resolve timing violations caused by the long interconnect routing delays between the SYSREF I/O pin and the register in the IP that detects the SYSREF signal, it is recommended to utilize multi-stages pipeline registers.
  • Deassert the link reset for the IP core two link clock cycles before starting the SYSREF pulse. Ensure transport layer is out-of-reset prior to SYSREF pulse generation. Refer to ADC-FPGA Subsystem Reset Sequence and FPGA-DAC Subsystem Reset Sequence for SYSREF sampling within the JESD204B reset sequence.