1. JESD204B IP Quick Reference 2. About the JESD204B Intel® FPGA IP 3. Getting Started 4. JESD204B IP Functional Description 5. JESD204B IP Deterministic Latency Implementation Guidelines 6. JESD204B IP Debug Guidelines 7. JESD204B Intel® FPGA IP User Guide Archives 8. Document Revision History for the JESD204B Intel® FPGA IP User Guide
3.1. Introduction to Intel® FPGA IP Cores 3.2. Installing and Licensing Intel® FPGA IP Cores 3.3. Intel® FPGA IP Evaluation Mode 3.4. Upgrading IP Cores 3.5. IP Catalog and Parameter Editor 3.6. Design Walkthrough 3.7. JESD204B Design Examples 3.8. JESD204B IP Design Considerations 3.9. JESD204B Intel® FPGA IP Parameters 3.10. JESD204B IP Component Files 3.11. JESD204B IP Testbench
The receiver block, which interfaces to ADC devices, receives the serial streams from one or more TX blocks and converts the streams into one or more sample streams.
The receiver performs the following functions:
- Data deserializer
- 8B/10B decoding
- Lane alignment
- Character replacement
- Data descrambling
Figure 13. Receiver Data Path Block Diagram
The receiver block includes the following modules:
- RX CSR—manages the configuration and status registers.
- RX_CTL—manages the SYNC_N signal, state machine that controls the data link layer states, LMFC, and also the buffer release, which is crucial for deterministic latency throughout the link.
- RX Scrambler and Data Link Layer—takes in 32 bits of data that decodes the ILAS, performs descrambling, character replacement as per the JESD204B specification, and error detection (code group error, frame and lane realignment error).