JESD204B Intel® FPGA IP User Guide

ID 683442
Date 7/20/2023
Document Table of Contents

2.4. IP Variation

The JESD204B IP has three core variations:
  • JESD204B MAC only
  • JESD204B PHY only
  • JESD204B MAC and PHY

In a subsystem where there are multiple ADC and DAC converters, you need to use the Intel® Quartus® Prime software to merge the transceivers and group them into the transceiver architecture. For example, to create two instances of the JESD204B TX IP with four lanes each and four instances of the JESD204B RX IP with two lanes each, you can apply one of the following options:

  • MAC and PHY option
    1. Generate JESD204B TX IP with four lanes and JESD204B RX IP with two lanes.
    2. Instantiate the desired components.
    3. Use the Intel® Quartus® Prime software to merge the PHY lanes.
  • MAC only and PHY only option—based on the configuration above, there are a total of eight lanes in duplex mode.
    1. Generate the JESD204B Duplex PHY with a total of eight lanes. (TX skew is reduced in this configuration as the channels are bonded).
    2. Generate the JESD204B TX MAC with four lanes and instantiate it two times.
    3. Generate the JESD204B RX MAC with two lanes and instantiate it four times.
    4. Create a wrapper to connect the JESD204B TX MAC and RX MAC with the JESD204B Duplex PHY.
Note: If the data rate for TX and RX is different, the transceiver does not allow duplex mode to generate a duplex PHY. In this case, you have to generate a RX-only PHY on the RX data rate and a TX-only PHY on the TX data rate.