5.3. Programmable RBD Offset
You must set a safe RBD offset value to ensure deterministic latency from one power cycle to another power cycle. Follow these steps to set a safe RBD offset value:
- Read the RBD count from the csr_rbd_count field in rx_status0 register. Record the value.
- Power cycle the JESD204B subsystem, which consists of the FPGA and converter devices.
- Read the RBD count again and record the value.
- Repeat steps 1 to 3 at least 5 times and record the RBD count values.
- Set the csr_rbd_offset accordingly with one LMFC count tolerance.
- Perform multiple power cycles and make sure lane deskew error does not occur using this RBD offset value.
The RBD count must be fairly consistent, within 2 counts variation from one power cycle to another power cycle. In the following examples, the parameter values are L > 1, F=1 and K=32. The legal values of the LMFC counter is 0 to ((FxK/4)-1), which is 0 to 7. In Early RBD Release Opportunity for Latest Arrival Lane Within One Local Multi Frame Scenario , the latest arrival lane variation falls within 1 local multiframe period. In this scenario, if latency is not a concern, you can leave the default value of csr_rbd_offset=0, which means the RBD elastic buffer is released at the LMFC boundary. In Early RBD Release Opportunity for Latest Arrival Lane Across Two Local Multi Frames Scenario , the latest arrival lane variation spans across 2 local multiframes; the latest arrival lane variation happens before and after the LMFC boundary. In this scenario, you need to configure the RBD offset correctly to avoid lane deskew error as indicated in bit 4 of rx_err0 register.
In the example above, lane deskew error happens if the sum of the difference of /R/ character’s LMFC count in the earliest arrival lane to the latest arrival lane, and the number of LMFC count up to the release of RBD elastic buffer exceeds the RBD elastic buffer size. If this is the root cause of lane deskew error, setting RBD offset is one of the techniques to overcome this issue. Not every RBD offset value is legal. Figure below illustrates the technique to decide the legal RBD offset value.
Because the IP core does not report the position of the earliest lane arrival with respect to the LMFC boundary, you must perform multiple power cycles to observe the RBD count and tune the RBD offset accordingly until no lane deskew error occurs. From the example in the figure above, the recommended RBD offset value is 4 or 5. Setting RBD offset to 1, 2 or 3 is illegal because this exceeds the RBD elastic buffer size for the F and K configurations.
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