Stratix V Avalon-MM Interface for PCIe Solutions: User Guide

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ID 683411
Date 5/21/2017
Public
Document Table of Contents
Document Table of Contents x
1. Datasheet 2. Getting Started with the Avalon-MM Design Example 3. Parameter Settings 4. 64- or 128-Bit Avalon-MM Interface to the Endpoint Application Layer 5. Registers 6. Interrupts for Endpoints 7. Error Handling A. PCI Express Protocol Stack 8. Transceiver PHY IP Reconfiguration 9. Throughput Optimization 10. Design Implementation 11. Additional Features 12. Debugging B. Frequently Asked Questions for PCI Express C. Lane Initialization and Reversal D. Document Revision History
1. Datasheet x
1.1. Stratix V Avalon-MM Interface for PCIe Datasheet 1.2. Features 1.3. Release Information 1.4. Device Family Support 1.5. Configurations 1.6. Design Examples 1.7. IP Core Verification 1.8. Resource Utilization 1.9. Recommended Speed Grades 1.10. Creating a Design for PCI Express
1.7. IP Core Verification x
1.7.1. Compatibility Testing Environment
2. Getting Started with the Avalon-MM Design Example x
2.1. Running Qsys 2.2. Generating the Example Design 2.3. Understanding Simulation Log File Generation 2.4. Running a Gate-Level Simulation 2.5. Simulating the Single DWord Design 2.6. Generating Synthesis Files 2.7. Creating a Quartus® Prime Project 2.8. Compiling the Design 2.9. Programming a Device 2.10. Understanding Channel Placement Guidelines
3. Parameter Settings x
3.1. System Settings 3.2. Base Address Register (BAR) Settings 3.3. Device Identification Registers 3.4. PCI Express and PCI Capabilities Parameters 3.5. Avalon Memory‑Mapped System Settings
3.4. PCI Express and PCI Capabilities Parameters x
3.4.1. Device Capabilities 3.4.2. Error Reporting 3.4.3. Link Capabilities 3.4.4. MSI and MSI-X Capabilities 3.4.5. Power Management
4. 64- or 128-Bit Avalon-MM Interface to the Endpoint Application Layer x
4.1. 32-Bit Non-Bursting Avalon-MM Control Register Access (CRA) Slave Signals 4.2. Bursting and Non-Bursting Avalon® -MM Module Signals 4.3. 64- or 128-Bit Bursting TX Avalon-MM Slave Signals 4.4. Clock Signals 4.5. Reset 4.6. Interrupts for Endpoints when Multiple MSI/MSI-X Support Is Enabled 4.7. Hard IP Status Signals 4.8. Physical Layer Interface Signals
4.7. Hard IP Status Signals x
4.7.1. Hard IP Reconfiguration Interface
4.8. Physical Layer Interface Signals x
4.8.1. Hard IP Status Extension 4.8.2. Serial Data Signals 4.8.3. PIPE Interface Signals 4.8.4. Test Signals
4.8.2. Serial Data Signals x
4.8.2.1. Physical Layout of Hard IP in Stratix V GX/GT/GS Devices 4.8.2.2. Channel Placement in Arria V GZ and Stratix V GX/GT/GS Devices
5. Registers x
5.1. Correspondence between Configuration Space Registers and the PCIe Specification 5.2. Type 0 Configuration Space Registers 5.3. Type 1 Configuration Space Registers 5.4. PCI Express Capability Structures 5.5. Intel-Defined VSEC Registers 5.6. CvP Registers 5.7. 64- or 128-Bit Avalon-MM Bridge Register Descriptions 5.8. Programming Model for Avalon-MM Root Port 5.9. Uncorrectable Internal Error Mask Register 5.10. Uncorrectable Internal Error Status Register 5.11. Correctable Internal Error Mask Register 5.12. Correctable Internal Error Status Register
5.7. 64- or 128-Bit Avalon-MM Bridge Register Descriptions x
5.7.1. Avalon-MM to PCI Express Interrupt Registers
5.7.1. Avalon-MM to PCI Express Interrupt Registers x
5.7.1.1. Avalon-MM to PCI Express Interrupt Status Registers 5.7.1.2. Avalon-MM to PCI Express Interrupt Enable Registers 5.7.1.3. PCI Express Mailbox Registers 5.7.1.4. Avalon-MM-to-PCI Express Address Translation Table 5.7.1.5. PCI Express to Avalon-MM Interrupt Status and Enable Registers for Endpoints 5.7.1.6. Avalon-MM Mailbox Registers 5.7.1.7. Control Register Access (CRA) Avalon-MM Slave Port
5.8. Programming Model for Avalon-MM Root Port x
5.8.1. Sending a Write TLP 5.8.2. Sending a Read TLP or Receiving a Non-Posted Completion TLP 5.8.3. Examples of Reading and Writing BAR0 Using the CRA Interface 5.8.4. PCI Express to Avalon-MM Interrupt Status and Enable Registers for Root Ports 5.8.5. Root Port TLP Data Registers
6. Interrupts for Endpoints x
6.1. Enabling MSI or Legacy Interrupts 6.2. Generation of Avalon-MM Interrupts 6.3. Interrupts for Endpoints Using the Avalon-MM Interface with Multiple MSI/MSI-X Support
7. Error Handling x
7.1. Physical Layer Errors 7.2. Data Link Layer Errors 7.3. Transaction Layer Errors 7.4. Error Reporting and Data Poisoning 7.5. Uncorrectable and Correctable Error Status Bits
A. PCI Express Protocol Stack x
A.1. Top-Level Interfaces A.2. Data Link Layer A.3. Physical Layer A.4. 32-Bit PCI Express Avalon-MM Bridge A.5. Completer Only Single Dword Endpoint
A.1. Top-Level Interfaces x
A.1.1. Avalon-MM Interface A.1.2. Clocks and Reset A.1.3. Transceiver Reconfiguration A.1.4. Interrupts A.1.5. PIPE
A.4. 32-Bit PCI Express Avalon-MM Bridge x
A.4.1. Avalon‑MM Bridge TLPs A.4.2. Avalon-MM-to-PCI Express Write Requests A.4.3. Avalon-MM-to-PCI Express Upstream Read Requests A.4.4. PCI Express-to-Avalon-MM Read Completions A.4.5. PCI Express-to-Avalon-MM Downstream Write Requests A.4.6. PCI Express-to-Avalon-MM Downstream Read Requests A.4.7. Avalon-MM-to-PCI Express Read Completions A.4.8. PCI Express-to-Avalon-MM Address Translation for 32-Bit Bridge A.4.9. Minimizing BAR Sizes and the PCIe Address Space A.4.10. Avalon® -MM-to-PCI Express Address Translation Algorithm for 32-Bit Addressing
A.5. Completer Only Single Dword Endpoint x
A.5.1. RX Block A.5.2. Avalon-MM RX Master Block A.5.3. TX Block A.5.4. Interrupt Handler Block
8. Transceiver PHY IP Reconfiguration x
8.1. Connecting the Transceiver Reconfiguration Controller IP Core 8.2. Transceiver Reconfiguration Controller Connectivity for Designs Using CvP
9. Throughput Optimization x
9.1. Throughput of Posted Writes 9.2. Throughput of Non-Posted Reads
10. Design Implementation x
10.1. Making Analog QSF Assignments Using the Assignment Editor 10.2. Making Pin Assignments to Assign I/O Standard to Serial Data Pins 10.3. Recommended Reset Sequence to Avoid Link Training Issues 10.4. SDC Timing Constraints
11. Additional Features x
11.1. Configuration over Protocol (CvP) 11.2. Autonomous Mode 11.3. ECRC
11.2. Autonomous Mode x
11.2.1. Enabling Autonomous Mode 11.2.2. Enabling CvP Initialization
11.3. ECRC x
11.3.1. ECRC on the RX Path 11.3.2. ECRC on the TX Path
12. Debugging x
12.1. Hardware Bring-Up Issues 12.2. Link Training 12.3. Use Third-Party PCIe Analyzer 12.4. BIOS Enumeration Issues
12.2. Link Training x
12.2.1. Debugging Link that Fails To Reach L0
D. Document Revision History x
D.1. Cyclone® V Avalon® Memory Mapped (Avalon-MM) Interface for PCIe* Solutions User Guide Revision History
1. Datasheet
2. Getting Started with the Avalon-MM Design Example
3. Parameter Settings
4. 64- or 128-Bit Avalon-MM Interface to the Endpoint Application Layer
5. Registers
6. Interrupts for Endpoints
7. Error Handling
A. PCI Express Protocol Stack
8. Transceiver PHY IP Reconfiguration
9. Throughput Optimization
10. Design Implementation
11. Additional Features
12. Debugging
B. Frequently Asked Questions for PCI Express
C. Lane Initialization and Reversal
D. Document Revision History

D.1. Cyclone® V Avalon® Memory Mapped (Avalon-MM) Interface for PCIe* Solutions User Guide Revision History

Date

Version

Changes Made

2020.03.19 17.1 Updated the reset sequence and descriptions in Reset and Clocks to show that reset_status is the output that can be used to reset the Application Layer logic.
2017.11.06 17.1 Made the following changes to the user guide.
  • Corrected Feature Comparison for all Hard IP for PCI Express IP Core table: The Avalon-MM interface does not automatically handle out-of-order completions.
2017.05.21 17.0 Made the following changes:
  • Corrected support for Completion with Data (CplD) in TLP Support Comparison for all Hard IP for PCI Express IP Cores. The Avalon-MM interface supports this TLP type.
  • Corrected default values for the Uncorrectable Internal Error Mask Register and Correctable Internal Error Mask Register registers.

  • Revised discussion of Application Layer Interrupt Handler Module to include legacy interrupt generation.

  • Added Configuration Space Register Access topic which shows the data that is multiplexed on the tl_cfg_ctl bus.

2016.10.31 16.1 Made the following changes:
  • Added topic explaining how to switch between serial and PIPE simulations.
  • Corrected the number of tags supported in the Feature Comparison for all Hard IP for PCI Express IP Cores table.
  • Added PCIe bifurcation to the Feature Comparison for all Hard IP for PCI Express IP Cores table. PCI bifurcation is not supported.
  • Corrected description and timing diagram for the tl_cfg* interface in the Configuration Space Register Access Timing topic.
  • Added instructions for turning on autonomous mode in the Quartus Prime software.
2016.05.01 16.0 Made the following changes:
  • Added Gen3 x2 128-bit interface with 125 MHz clock to the coreclkout_hip Application Layer Clock Frequency for All Combinations of Link Width, Data Rate and Application Layer Interface Widths table.
  • Clarified optimal read request size for typical systems that include the Avalon-MM TX slave interface.
  • Added figure for TX 3-dword header with qword aligned data
  • Added simulation support for Gen3 PIPE mode using the ModelSim, VCS, and NCSim simulators.
  • Corrected minor errors and typos.
2015.11.30 15.1 Made the following changes to the user guide:
  • Added TX_FIFO_EMPTY bit to the PCI Express to Avalon-MM Interrupt Status register for Legacy Endpoints only. This bit is set when the TX internal buffer is ready.
  • Enhanced the descriptions in Avalon-MM-to-PCI Express Address Translation Table.
  • Enhanced the definition of npor.
  • Added definition of Address width of accessible PCIe memory space in Parameter Settings chapter.
  • Added description of the Altera PCIe Reconfig Driver in the Connecting the Transceiver Reconfiguration Controller IP Core topic.
  • Clarified Application Layer requirements for multiple and single MSI and MSI-X support.
  • Corrected width of AVL_IRQ. It is 16 bits.
  • Added the following restriction for 128-bit Avalon-MM bridge. Supported patterns for byte enables must be at the dword granularity.
  • Clarified Avalon-MM addressing for various data widths.
  • Added signal definitions for currentspeed and tl_cfg_ctl which were missing.
  • Added note explaining that the Getting Started design examples do not generate all the files necessary to download to an Altera FPGA Development Kit. Provided link to AN456 PCI Express High Performance Reference Design that includes all necessary files.
2014.12.15 14.1 Made the following changes to the user guide:
  • Added statement that the bottom left hard IP block includes the CvP functionality for flip chip packages. For other package types, the CvP functionality is in the bottom right block.
  • Corrected bit definitions for CvP Status register.
  • Updated definition of CVP_NUMCLKS in the CvP Mode Control register.
  • Added definitions for test_in[2], test_in[6] and test_in[7].
  • Added note that for Root Ports, when the Slot Power register is enabled, the Command Completed Interrupt Enable bit of the Slot Control register remains Read/Write. It should be hardwired to 1'b0.
  • Removed requirement that TxsWrite_i be asserted continuously throughout a write burst. TxsWrite_i may be deasserted and reasserted during a burst.
  • Added figure showing connectivity for the Transceiver Reconfiguration Controller and Altera PCIe Reconfig Driver IP Cores to the Getting Started chapter.
  • Removed Maximum and High settings from the RX Buffer credit allocation -performance for received requests setting. These settings are not available for the Avalon-MM interface and could lead to data corruption.
  • Revised Receiving a Completion TLP under Programming Model for Avalon-MM Root Port to cover read and non-posted completions.
2014.06.30 14.0

Added the following features to the Stratix V Avalon-MM Hard IP for PCI Express:

  • Added access to selected Configuration Space registers and link status registers through the optional Control Register Access (CRA) Avalon-MM slave port.
  • Added simulation log file, altpcie_monitor_sv_dlhip_tlp_file_log.log, that is automatically generated in your simulation directory. To simulation in the Quartus II 14.0 software release, you must regenerate your IP core to create the supporting monitor file the generates altpcie_monitor_sv_dlhip_tlp_file_log.log. Refer to Understanding Simulation Dump File Generation for details.
  • Added parameter to create a reset pulse at power-up when the soft reset controller is enabled.
  • Added optional hard IP status bus that includes signals necessary to connect the Transceiver Reconfiguration Controller IP Core.
  • Added optional hard IP status extension bus which includes signals that are useful for debugging, including: link training, status, error, and Configuration Space signals.
  • Added support for 64-bit addressing, making address translation unnecessary.
  • Added parameters to enable 256 completion tags with completion tag checking performed in Application Layer.
  • Simulation support for Phase 2 and Phase 3 equalization when requested by third-party BFM.
  • Increased CRA address to 14 bits from 12 bits.
  • For txs_byteenable[<w>-1:0], added restrictions on the legal patterns of enabled and disabled bytes.
  • Clarified the behavior of the txs_waitrequest signal.

Made the following changes to the user guide:

  • Removed all references to the Avalon-MM interrupt vector register. This register is not used.
  • Corrected addresses for Vendor ID, Device ID, Revision ID, Class Code, Subsystem Vendor ID and Subsystem Device ID in Reconfigurable Read-Only Registers.
  • Corrected values for Maximum payload size parameter. The sizes available are 128 or 256 bytes.
  • Corrected frequency range for hip_reconfig_clk. It should be 100-125 MHz.
  • Removed section on Hard IP Reconfiguration. This feature is only available when you select the Avalon-ST interface.
  • Enhanced definition of Device ID and Sub-system Vendor ID to say that these registers are only valid in the Type 0 (Endpoint) Configuration Space.
  • Simplified the Getting Started chapter. It copies the Gen2 x4 example from the install directory and does not include step-by-step instructions to recreate the design.
  • Corrected frequencies of pclk in Reset and Clocks chapter.
  • Added Next Steps in Creating a Design for PCI Express to Datasheet chapter.
  • Removed txdatavalid0 signal from the PIPE interface. This signal is not available.
  • Removed references to the MegaWizard® Plug-In Manager. In 14.0 the IP Parameter Editor Powered by Qsys has replaced the MegaWizard Plug-In Manager.
  • Removed the Transaction Layer Protocol Details chapter. This information only applies to the Avalon-ST interface.
  • Added link to a Knowledge Base Solution that shows how to observe the test_in bus for debugging.
  • Corrected channel placement diagrams for Gen3 x2 and Gen3 x4. The CMU PLL should be shown in the Channel 4 location. For Gen3 x2, the second data channel is Ch1. For Gen3 x4, the data channels are Ch0 - Ch3.
  • Corrected figure showing physical placement of PCIe Hard IP modules for Arria V GZ devices.
  • Added definition for test_in[6] and link to Knowledge Base Solution on observing the PIPE interface signals on the test_out bus.
  • Clarified that the Avalon-MM Bridge does not generate out-of-order Avalon-MM-to-PCI Express Read Completions even to different BARs.
  • Added register definition for Avalon-MM Interrupt Vector register (0x0060), missing from previous release.
  • Removed references to Gen2 x1 62.5 MHz configuration. This configuration is not supported.
  • Removed statement that Gen1 and Gen2 designs do not require transceiver reconfiguration. Gen1 and Gen2 designs may require transceiver reconfiguration to improve signal quality.
  • For Stratix V and Arria V GZ devices, corrected channel placement diagrams for x8. Both Gen3 Channel Placement Using the CMU and ATX PLLs and Gen1 and Gen2 Channel Placement Using the ATX PLL show the ATX PLL1 in bank 1 being used. However, ATX PLL 1 in bank 0 is actually used.
  • Updated Power Supply Voltage Requirements table.
  • For Arria 10 devices, updated Physical Placement of the Arria 10 Hard IP for PCIe IP and Channels to show GT devices instead of GX devices.
2013.12.20 13.1 Made the following changes:
  • Divided user guide into 3 separate documents by interface type.
  • Added Design Implementation chapter.
  • In the Debugging chapter, removed section explaining how to turn off the scrambler for Gen3 because it does not work.
  • In the Debugging chapter, corrected filename that you must change to reduce counter values in simulation.
  • In Getting Started with the Avalon-MM Hard IP for PCI Express chapter, corrected connects for the Transceiver Reconfiguration Controller IP Core reset signal, alt_xcvr_reconfig_0 mgmt_rst_reset. This reset input connects to clk_0 clk_reset.
  • In Transaction Layer Routing Rules and Programming Model for Avalon-MM Root Port added the fact that Type 0 Configuration Requests sent to the Root Port are not filtered by the device number. Application Layer software must filter out requests for device number greater than 0.
  • Added illustration showing the location of the Hard IP Cores in the Stratix V devices.
  • Added limitation for rxm_irq_<n>[<m>:0]when interrupts are received on consecutive cycles.
  • Corrected description of cfg_prm_cmr. It is the Base/Primary Command register for the PCI Configuration Space.
  • Revised channel placement illustrations.

2013.05.06

13.0

  • Added preliminary support for a Avalon-MM 256-Bit Hard IP for PCI Express that is capable of running at the Gen3 ×8 data rate. This new IP Core. Refer to the Avalon-MM 256-Bit Hard IP for PCI Express User Guide for more information.
  • Added Gen3 PIPE simulation support.
  • Added support for 64-bit address in the Avalon-MM Hard IP for PCI Express IP Core, making address translation unnecessary
  • Added instructions for running the Single Dword variant.
  • Timing models are now final.
  • Updated the definition of refclk to include constraints when CvP is enabled.
  • Added section covering clock connectivity for reconfiguration when CvP is enabled.
  • Corrected access field in Root Port TLP Data registers.
  • Added Getting Started chapter for Configuration Space Bypass mode.
  • Added signal and register descriptions for the Gen3 PIPE simulation.
  • Added 64-bit addressing for the Avalon-MM IP Cores for PCI Express.
  • Changed descriptions of rx_st_err[1:0], tx_st_err[1:0], rx_st_valid[1:0], and tx_st_valid[1:0] buses. Bit 1 is not used.
  • Corrected definitions of RP_RXCPL_STATUS.SOP and RP_RXCPL_STATUS.EOP bits. SOP is 0x2010, bit[0] and EOP is 0x2010, bit[1].
  • Improved explanation of relaxed ordering of transactions and provided examples.
  • Revised discussion of Transceiver Reconfiguration Controller IP Core. Offset cancellation is not required for Gen1 or Gen2 operation.
  • Removed reconfig_busy port from connect between PHY IP Core for PCI Express and the Transceiver Reconfiguration Controller in the Altera Transceiver Reconfiguration Controller Connectivity figure. The Transceiver Reconfiguration Controller drives reconfig_busy port to the Altera PCIe Reconfig Driver.

2011.07.30

11.01

Corrected typographical errors.

2011.05.06

11.0

First release.

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