A.5. Completer Only Single Dword Endpoint
The completer only single dword endpoint is intended for applications that use the PCI Express protocol to perform simple read and write register accesses from a host CPU. The completer only single dword endpoint is a hard IP implementation available for Platform Designer systems, and includes an Avalon‑MM interface to the Application Layer. The Avalon‑MM interface connection in this variation is 32 bits wide. This endpoint is not pipelined; at any time a single request can be outstanding.
The completer-only single dword endpoint supports the following requests:
- Read and write requests of a single dword (32 bits) from the Root Complex
- Completion with Completer Abort status generation for other types of non‑posted requests
- INTX or MSI support with one Avalon‑MM interrupt source
The above figure shows the that completer‑only single dword endpoint connects to a PCI Express Root Complex. A bridge component includes the Stratix V Hard IP for PCI Express TX and RX blocks, an Avalon‑MM RX master, and an interrupt handler. The bridge connects to the FPGA fabric using an Avalon‑MM interface. The following sections provide an overview of each block in the bridge.
Avalon-MM RX Master Block
Interrupt Handler Block
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