A.4. 32-Bit PCI Express Avalon-MM Bridge
The Avalon‑MM Stratix V Hard IP for PCI Express includes an Avalon-MM bridge module that connects the Hard IP to the interconnect fabric. The bridge facilitates the design of Endpoints and Root Ports that include Platform Designer components.
The Avalon-MM bridge provides three possible Avalon‑MM ports: a bursting master, an optional bursting slave, and an optional non-bursting slave. The Avalon-MM bridge comprises the following three modules:
- TX Slave Module—This optional 64- or 128‑bit bursting, Avalon-MM dynamic addressing slave port propagates read and write requests of up to 4 KB in size from the interconnect fabric to the PCI Express link. The bridge translates requests from the interconnect fabric to PCI Express request packets.
- RX Master Module—This 64- or 128‑bit bursting Avalon-MM master port propagates PCI Express requests, converting them to bursting read or write requests to the interconnect fabric.
- Control Register Access (CRA) Slave Module—This optional, 32-bit Avalon-MM dynamic addressing slave port provides access to internal control and status registers from upstream PCI Express devices and external Avalon-MM masters. Implementations that use MSI or dynamic address translation require this port. The CRA port supports single dword read and write requests. It does not support bursting.
When you select the Single dword completer for the Avalon‑MM Hard IP for PCI Express, Platform Designer substitutes an unpipelined, 32‑bit RX master port for the 64‑ or 128‑bit full‑featured RX master port. The following figure shows the block diagram of a full-featured PCI Express Avalon-MM bridge.
- Type 0 and Type 1 vendor-defined incoming messages are discarded.
- Completion-to-a-flush request is generated, but not propagated to the interconnect fabric.
For End Points, each PCI Express base address register (BAR) in the Transaction Layer maps to a specific, fixed Avalon-MM address range. You can use separate BARs to map to various Avalon-MM slaves connected to the RX Master port. In contrast to Endpoints, Root Ports do not perform any BAR matching and forward the address to a single RX Avalon-MM master port.
Avalon‑MM Bridge TLPs
Avalon-MM-to-PCI Express Write Requests
Avalon-MM-to-PCI Express Upstream Read Requests
PCI Express-to-Avalon-MM Read Completions
PCI Express-to-Avalon-MM Downstream Write Requests
PCI Express-to-Avalon-MM Downstream Read Requests
Avalon-MM-to-PCI Express Read Completions
PCI Express-to-Avalon-MM Address Translation for 32-Bit Bridge
Minimizing BAR Sizes and the PCIe Address Space
Avalon -MM-to-PCI Express Address Translation Algorithm for 32-Bit Addressing
Did you find the information on this page useful?