Stratix V Avalon-MM Interface for PCIe Solutions: User Guide

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ID 683411
Date 5/21/2017
Public
Document Table of Contents
Document Table of Contents x
1. Datasheet 2. Getting Started with the Avalon-MM Design Example 3. Parameter Settings 4. 64- or 128-Bit Avalon-MM Interface to the Endpoint Application Layer 5. Registers 6. Interrupts for Endpoints 7. Error Handling A. PCI Express Protocol Stack 8. Transceiver PHY IP Reconfiguration 9. Throughput Optimization 10. Design Implementation 11. Additional Features 12. Debugging B. Frequently Asked Questions for PCI Express C. Lane Initialization and Reversal D. Document Revision History
1. Datasheet x
1.1. Stratix V Avalon-MM Interface for PCIe Datasheet 1.2. Features 1.3. Release Information 1.4. Device Family Support 1.5. Configurations 1.6. Design Examples 1.7. IP Core Verification 1.8. Resource Utilization 1.9. Recommended Speed Grades 1.10. Creating a Design for PCI Express
1.7. IP Core Verification x
1.7.1. Compatibility Testing Environment
2. Getting Started with the Avalon-MM Design Example x
2.1. Running Qsys 2.2. Generating the Example Design 2.3. Understanding Simulation Log File Generation 2.4. Running a Gate-Level Simulation 2.5. Simulating the Single DWord Design 2.6. Generating Synthesis Files 2.7. Creating a Quartus® Prime Project 2.8. Compiling the Design 2.9. Programming a Device 2.10. Understanding Channel Placement Guidelines
3. Parameter Settings x
3.1. System Settings 3.2. Base Address Register (BAR) Settings 3.3. Device Identification Registers 3.4. PCI Express and PCI Capabilities Parameters 3.5. Avalon Memory‑Mapped System Settings
3.4. PCI Express and PCI Capabilities Parameters x
3.4.1. Device Capabilities 3.4.2. Error Reporting 3.4.3. Link Capabilities 3.4.4. MSI and MSI-X Capabilities 3.4.5. Power Management
4. 64- or 128-Bit Avalon-MM Interface to the Endpoint Application Layer x
4.1. 32-Bit Non-Bursting Avalon-MM Control Register Access (CRA) Slave Signals 4.2. Bursting and Non-Bursting Avalon® -MM Module Signals 4.3. 64- or 128-Bit Bursting TX Avalon-MM Slave Signals 4.4. Clock Signals 4.5. Reset 4.6. Interrupts for Endpoints when Multiple MSI/MSI-X Support Is Enabled 4.7. Hard IP Status Signals 4.8. Physical Layer Interface Signals
4.7. Hard IP Status Signals x
4.7.1. Hard IP Reconfiguration Interface
4.8. Physical Layer Interface Signals x
4.8.1. Hard IP Status Extension 4.8.2. Serial Data Signals 4.8.3. PIPE Interface Signals 4.8.4. Test Signals
4.8.2. Serial Data Signals x
4.8.2.1. Physical Layout of Hard IP in Stratix V GX/GT/GS Devices 4.8.2.2. Channel Placement in Arria V GZ and Stratix V GX/GT/GS Devices
5. Registers x
5.1. Correspondence between Configuration Space Registers and the PCIe Specification 5.2. Type 0 Configuration Space Registers 5.3. Type 1 Configuration Space Registers 5.4. PCI Express Capability Structures 5.5. Intel-Defined VSEC Registers 5.6. CvP Registers 5.7. 64- or 128-Bit Avalon-MM Bridge Register Descriptions 5.8. Programming Model for Avalon-MM Root Port 5.9. Uncorrectable Internal Error Mask Register 5.10. Uncorrectable Internal Error Status Register 5.11. Correctable Internal Error Mask Register 5.12. Correctable Internal Error Status Register
5.7. 64- or 128-Bit Avalon-MM Bridge Register Descriptions x
5.7.1. Avalon-MM to PCI Express Interrupt Registers
5.7.1. Avalon-MM to PCI Express Interrupt Registers x
5.7.1.1. Avalon-MM to PCI Express Interrupt Status Registers 5.7.1.2. Avalon-MM to PCI Express Interrupt Enable Registers 5.7.1.3. PCI Express Mailbox Registers 5.7.1.4. Avalon-MM-to-PCI Express Address Translation Table 5.7.1.5. PCI Express to Avalon-MM Interrupt Status and Enable Registers for Endpoints 5.7.1.6. Avalon-MM Mailbox Registers 5.7.1.7. Control Register Access (CRA) Avalon-MM Slave Port
5.8. Programming Model for Avalon-MM Root Port x
5.8.1. Sending a Write TLP 5.8.2. Sending a Read TLP or Receiving a Non-Posted Completion TLP 5.8.3. Examples of Reading and Writing BAR0 Using the CRA Interface 5.8.4. PCI Express to Avalon-MM Interrupt Status and Enable Registers for Root Ports 5.8.5. Root Port TLP Data Registers
6. Interrupts for Endpoints x
6.1. Enabling MSI or Legacy Interrupts 6.2. Generation of Avalon-MM Interrupts 6.3. Interrupts for Endpoints Using the Avalon-MM Interface with Multiple MSI/MSI-X Support
7. Error Handling x
7.1. Physical Layer Errors 7.2. Data Link Layer Errors 7.3. Transaction Layer Errors 7.4. Error Reporting and Data Poisoning 7.5. Uncorrectable and Correctable Error Status Bits
A. PCI Express Protocol Stack x
A.1. Top-Level Interfaces A.2. Data Link Layer A.3. Physical Layer A.4. 32-Bit PCI Express Avalon-MM Bridge A.5. Completer Only Single Dword Endpoint
A.1. Top-Level Interfaces x
A.1.1. Avalon-MM Interface A.1.2. Clocks and Reset A.1.3. Transceiver Reconfiguration A.1.4. Interrupts A.1.5. PIPE
A.4. 32-Bit PCI Express Avalon-MM Bridge x
A.4.1. Avalon‑MM Bridge TLPs A.4.2. Avalon-MM-to-PCI Express Write Requests A.4.3. Avalon-MM-to-PCI Express Upstream Read Requests A.4.4. PCI Express-to-Avalon-MM Read Completions A.4.5. PCI Express-to-Avalon-MM Downstream Write Requests A.4.6. PCI Express-to-Avalon-MM Downstream Read Requests A.4.7. Avalon-MM-to-PCI Express Read Completions A.4.8. PCI Express-to-Avalon-MM Address Translation for 32-Bit Bridge A.4.9. Minimizing BAR Sizes and the PCIe Address Space A.4.10. Avalon® -MM-to-PCI Express Address Translation Algorithm for 32-Bit Addressing
A.5. Completer Only Single Dword Endpoint x
A.5.1. RX Block A.5.2. Avalon-MM RX Master Block A.5.3. TX Block A.5.4. Interrupt Handler Block
8. Transceiver PHY IP Reconfiguration x
8.1. Connecting the Transceiver Reconfiguration Controller IP Core 8.2. Transceiver Reconfiguration Controller Connectivity for Designs Using CvP
9. Throughput Optimization x
9.1. Throughput of Posted Writes 9.2. Throughput of Non-Posted Reads
10. Design Implementation x
10.1. Making Analog QSF Assignments Using the Assignment Editor 10.2. Making Pin Assignments to Assign I/O Standard to Serial Data Pins 10.3. Recommended Reset Sequence to Avoid Link Training Issues 10.4. SDC Timing Constraints
11. Additional Features x
11.1. Configuration over Protocol (CvP) 11.2. Autonomous Mode 11.3. ECRC
11.2. Autonomous Mode x
11.2.1. Enabling Autonomous Mode 11.2.2. Enabling CvP Initialization
11.3. ECRC x
11.3.1. ECRC on the RX Path 11.3.2. ECRC on the TX Path
12. Debugging x
12.1. Hardware Bring-Up Issues 12.2. Link Training 12.3. Use Third-Party PCIe Analyzer 12.4. BIOS Enumeration Issues
12.2. Link Training x
12.2.1. Debugging Link that Fails To Reach L0
D. Document Revision History x
D.1. Cyclone® V Avalon® Memory Mapped (Avalon-MM) Interface for PCIe* Solutions User Guide Revision History
1. Datasheet
2. Getting Started with the Avalon-MM Design Example
3. Parameter Settings
4. 64- or 128-Bit Avalon-MM Interface to the Endpoint Application Layer
5. Registers
6. Interrupts for Endpoints
7. Error Handling
A. PCI Express Protocol Stack
8. Transceiver PHY IP Reconfiguration
9. Throughput Optimization
10. Design Implementation
11. Additional Features
12. Debugging
B. Frequently Asked Questions for PCI Express
C. Lane Initialization and Reversal
D. Document Revision History

3.1. System Settings

Table 10.  System Settings for PCI Express

Parameter

Value

Description

Number of Lanes

x1, x2, x4, x8

Specifies the maximum number of lanes supported.

Lane Rate

Gen1 (2.5 Gbps)

Gen2 (2.5/5.0 Gbps)

Gen3 (2.5/5.0/8.0 Gbps) 

Specifies the maximum data rate at which the link can operate.

Port type

Native Endpoint

Root Port

Specifies the port type. Intel recommends Native Endpoint for all new Endpoint designs. Select Legacy Endpoint only when you require I/O transaction support for compatibility.

The Endpoint stores parameters in the Type 0 Configuration Space. The Root Port stores parameters in the Type 1 Configuration Space.

RX Buffer credit allocation -performance for received requests

Minimum

Low

Balanced

Determines the allocation of posted header credits, posted data credits, non-posted header credits, completion header credits, and completion data credits in the 16 KBytes RX buffer. The settings allow you to adjust the credit allocation to optimize your system. The credit allocation for the selected setting displays in the message pane.

Refer to the Throughput Optimization chapter in the Stratix V Avalon-ST Interface for PCIe Solutions User Guidefor more information about optimizing performance.

The Message window dynamically updates the number of credits for Posted, Non‑Posted Headers and Data, and Completion Headers and Data as you change this selection.

  • Minimum—configures the minimum PCIe specification allowed for non-posted and posted request credits, leaving most of the RX Buffer space for received completion header and data. Select this option for variations where application logic generates many read requests and only infrequently receives single requests from the PCIe link.
  • Low—configures a slightly larger amount of RX Buffer space for non-posted and posted request credits, but still dedicates most of the space for received completion header and data. Select this option for variations where application logic generates many read requests and infrequently receives small bursts of requests from the PCIe link. This option is recommended for typical endpoint applications where most of the PCIe traffic is generated by a DMA engine that is located in the endpoint application layer logic.
  • Balanced—configures approximately half the RX Buffer space to received requests and the other half of the RX Buffer space to received completions. Select this option for variations where the received requests and received completions are roughly equal.

Reference clock frequency

100 MHz

125 MHz

The PCI Express Base Specification 3.0 requires a 100 MHz ±300 ppm reference clock. The 125 MHz reference clock is provided as a convenience for systems that include a 125 MHz clock source. For more information about Gen3 operation, refer to 4.3.8 Refclk Specifications for 8.0 GT/sin the specification.

For Gen3, Intel recommends using a common reference clock (0 ppm) because when using separate reference clocks (non 0 ppm), the PCS occasionally must insert SKP symbols, potentially causes the PCIe link to go to recovery. Stratix V PCIe Hard IP in Gen1 or Gen2 modes are not affected by this issue. Systems using the common reference clock (0 ppm) are not affected by this issue. The primary repercussion of this is a slight decrease in bandwidth. On Gen3 x8 systems, this bandwidth impact is negligible. If non 0 ppm mode is required, so that separate reference clocks are being used, please contact Intel for further information and guidance.

Use 62.5 MHz application clock

On/Off

This mode is only available only for Gen1 ×1.

Enable configuration via PCI Express (CvP)

On/Off

When On, the Quartus® Prime software places the Endpoint in the location required for configuration via protocol (CvP). For more information about CvP, click the Configuration via Protocol (CvP) link below.

Use ATX PLL On/Off When enabled, the Hard IP for PCI Express uses the ATX PLL instead of the CMU PLL. For other configurations, using the ATX PLL instead of the CMU PLL reduces the number of transceiver channels that are necessary. This option requires the use of the soft reset controller and does not support the CvP flow.
Enable Hard IP reset pulse at power-up when using the soft reset controller

On/Off

When On, the soft reset controller generates a pulse at power up to reset the Hard IP. This pulse ensures that the Hard IP is reset after programming the device, regardless of the behavior of the dedicated PCI Express reset pin, perstn. This option is available for Gen2 and Gen3 designs that use a soft reset controller.
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