Stratix V Avalon-MM Interface for PCIe Solutions: User Guide

ID 683411
Date 5/21/2017
Public
Document Table of Contents
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2.4. Running a Gate-Level Simulation

The PCI Express testbenches run simulations at the register transfer level (RTL). However, it is possible to create your own gate-level simulations. Contact your Intel Sales Representative for instructions and an example that illustrates how to create a gate-level simulation from the RTL testbench.