Stratix V Avalon-MM Interface for PCIe Solutions: User Guide

ID 683411
Date 5/21/2017
Public
Document Table of Contents

10.3. Recommended Reset Sequence to Avoid Link Training Issues

Successful link training can only occur after the FPGA is configured and the Transceiver Reconfiguration Controller IP Core has dynamically reconfigured SERDES analog settings to optimize signal quality. For designs using CvP, link training occurs after configuration of the I/O ring and Hard IP for PCI Express IP Core. Refer to Reset Sequence for Hard IP for PCI Express IP Core and Application Layer for a description of the key signals that control reset, control dynamic reconfiguration, and link training. Intel recommends separate control of reset signals for the Endpoint and Root Port. Successful reset sequence includes the following steps: