Stratix V Avalon-MM Interface for PCIe Solutions: User Guide

ID 683411
Date 5/21/2017
Document Table of Contents

A.4.3. Avalon-MM-to-PCI Express Upstream Read Requests

The PCI Express Avalon-MM bridge converts read requests from the system interconnect fabric to PCI Express read requests with 32-bit or 64‑bit addresses based on the address translation configuration, the request address, and the maximum read size.

The Avalon-MM TX slave interface of a PCI Express Avalon‑MM bridge can receive read requests with burst sizes of up to 512 bytes sent to any address. However, the bridge limits read requests sent to the PCI Express link to a maximum of 256 bytes. Additionally, the bridge must prevent each PCI Express read request packet from crossing a 4 KB address boundary. Therefore, the bridge may split an Avalon-MM read request into multiple PCI Express read packets based on the address and the size of the read request.

Avalon-MM bridge supports up to eight outstanding reads from Avalon-MM interface. Once the bridge has eight outstanding read requests, the txs_waitrequest signal is asserted to block additional read requests. When a read request completes, the Avalon-MM bridge can accept another request.

For Avalon-MM read requests with a burst count greater than one, all byte enables must be asserted. There are no restrictions on byte enables for Avalon-MM read requests with a burst count of one. If more than 1 dword is enabled, the enabled dwords must be contiguous. The following patterns are legal:
  • 16'hF000
  • 16'h0F00
  • 16'h00F0
  • 16'h000F
  • 16'hFF00
  • 16'h0FF0
  • 16'h00FF
  • 16'hFFF0
  • 16'h0FFF
  • 16'hFFFF
An invalid Avalon-MM request can adversely affect system functionality, resulting in a completion with the abort status set. An example of an invalid request is one with an incorrect address.