Serial Lite IV Intel® Agilex™ FPGA IP Design Example User Guide

ID 683391
Date 11/01/2021
Public

3.7. Serial Lite IV IP Toolkit

The Serial Lite IV IP toolkit is an inspection tool that monitors the status of a Serial Lite IV IP link and provides a step-by-step guide for the IP link initialization sequences.

The Serial Lite IV IP toolkit mainly monitors the following:
  • MAC link up status
  • Hardened Custom PCS lane alignment status
  • Clock data recovery (CDR) lock
  • Traffic generator and checker statistics
  • Forward Error Correction (FEC) statistics

The IP link initialization sequences guide also includes CSRs to monitor and log errors that occur during the operation.

Note: The toolkit uses hardened customer PCS core and MAC output ports to provide real-time link status. Therefore, the toolkit can only work with the design files with the settings you set during the design example generation. Any modifications to the generated design files may cause the toolkit to work incorrectly.

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