Serial Lite IV Intel® Agilex™ FPGA IP Design Example User Guide

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ID 683391
Date 11/01/2021
Public

3.2.1. Traffic Generator

The traffic generator generates traffic in a deterministic format to verify that data is transmitted correctly across the link. The traffic consists of sets of sample words, one for each lane on the link, that the traffic checker transmits to the source user interface.

If you configure the Serial Lite IV IP in full mode, the traffic generator also asserts the tx_is_usr_cmd signal at random to specify the packet is from user data for testing purposes. The Serial Lite IV IP asserts the num_valid_bytes_eob control signal to signify the number of valid bytes of the burst packet.

Figure 7. Traffic Generator Sample Word FormatThis figure shows the format of the sample words generated for each lane.
Table 7.  Traffic Generator Sample Word Fields

Field

Bits

Description

Word ID

63–59

Contains a static value to distinguish which 64-bit word on the user interface that this sample was presented on. The Word ID value ranges from 0 to (lanes – 1).

Burst Count

58–32

Tracks the number of bursts used to transfer the sample data. This field value starts with one after reset and is incremented each time the start_of_burst signal asserts on the source user interface.

Word Count

31–0

Tracks the number of valid sample words that the traffic generator transfers, across all bursts, to the source user interface.

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