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1. About the Serial Lite IV Intel® Agilex™ FPGA IP Design Example User Guide
2. Quick Start Guide
3. Detailed Description for Serial Lite IV Design Example
4. Serial Lite IV Intel® Agilex™ FPGA IP Design Example User Guide Archives
5. Document Revision History for the Serial Lite IV Intel® Agilex® FPGA IP Design Example User Guide
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3.4.2. Hardware Testing Result for Full Transfer Mode
The following are samples of hardware testing results for each design example variant.
Figure 14. Example of System Console Printout for PAM4 with RS-FEC Enabled
Figure 15. Example of System Console Printout for NRZ with RS-FEC Enabled
Note: The NRZ without RS-FEC enabled variant (RS-FEC mode: 0) has similar system console printout.