2.3.2. Directory Structure
The following diagrams show the directories that contain the generated files for the design example.
|ed_sim/tb_components||The directory that contains the testbench files.|
|ed_sim/common||The directory that contains the .tcl scripts for all the simulators.|
The directories that contain the simulation scripts. These directories also serve as a working area for the simulators.
|ed_sim/seriallite4_dup||The directory that contains the design example simulation source files.|
|ed_sim/seriallite4_dup.ip||IP-XACT representation of the design.|
|ed_synth/seriallite_iv_streaming_demo.qpf||Intel® Quartus® Prime Pro Edition project file.|
|ed_synth/seriallite_iv_streaming_demo.qsf||Intel® Quartus® Prime Pro Edition settings file.|
|ed_synth/seriallite_iv_streaming_demo.sdc||Synopsys Design Constraints (SDC) file.|
|ed_synth/src||The directory that contains the design example synthesizable components.|
|ed_synth/src/seriallite_iv_streaming_demo.v||Design example top-level HDL.|
|The directory for each synthesizable component including Platform Designer-generated IPs, such as Demo Management and Demo Control modules.|
|ed_hwtest||The directory that contains the design example hardware setup files.|
|ed_hwtest/Readme.txt||Instruction file to download the generated design example on the development kit.|
|ed_hwtest/system_console||The directory that contains system console scripts that provide useful commands to read statistics and to test the hardware design.|
|ed_hwtest/sliv_ip_toolkit_agilex||The folder that contains the scripts to invoke the Serial Lite IV IP toolkit for Intel® Agilex™ devices. This toolkit is a user-friendly GUI that provides step-by-step link initialization and debugging.|
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