1. About the Serial Lite IV Intel® Agilex™ FPGA IP Design Example User Guide
|Intel® Quartus® Prime Design Suite 21.3|
|IP Version 1.3.1|
This document describes features, usage guidelines, and functional description of the Serial Lite IV Intel® FPGA IP design examples using E-tile transceivers in Intel® Agilex® devices.
- Design architects to make IP selection during system level design planning phase.
- Hardware designers when integrating the IP into their system level design.
- Validation engineers during system level simulation and hardware validation phase.
|Serial Lite IV Intel® FPGA IP User Guide||
This user guide provides IP features, architecture description, steps to generate, and guidelines to design the Serial Lite IV Intel® FPGA IP using the E-tile transceivers.
|Serial Lite IV Intel® Stratix® 10 Design Example User Guide||This document provides features, usage guidelines, and functional descriptions of the Serial Lite IV Intel® FPGA IP design examples in Intel® Stratix® 10 devices.|
|E-tile Hard IP User Guide: E-tile Hard IP for Ethernet and E-Tile CPRI PHY Intel FPGA IPs||
This document describes the features, functionality, and guidelines of the E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IP cores in Intel® Stratix® 10 and Intel® Agilex™ devices.
|Intel® Agilex™ Device Data Sheet||
This document describes the electrical characteristics, switching characteristics, configuration specifications, and timing for Intel® Agilex™ devices.
|E-Tile Transceiver PHY User Guide||
This document describes the features, functionality, and guidelines for the E-Tile Transceiver PHY in Intel® Stratix® 10 and Intel® Agilex™ devices.
|Intel Agilex F-Series Transceiver SoC Development Kit User Guide||
This document describes the features, functionality, and guidelines for the Intel® Agilex™ F-Series Transceiver SoC Development Kit.
|Serial Lite IV Intel® FPGA IP Release Notes||
This document lists the changes made in the IP for a particular release.
Acronyms and Glossary
|RS-FEC||Reed-Solomon Forward Error Correction|
|PMA||Physical Medium Attachment|
|PAM4||Pulse-Amplitude Modulation 4-Level|
|PCS||Physical Coding Sublayer|
|MII||Media Independent Interface|
|XGMII||10 Gigabit Media Independent Interface|
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