Serial Lite IV Intel® Agilex™ FPGA IP Design Example User Guide

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ID 683391
Date 11/01/2021
Public

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Document Table of Contents
Document Table of Contents x
1. About the Serial Lite IV Intel® Agilex™ FPGA IP Design Example User Guide 2. Quick Start Guide 3. Detailed Description for Serial Lite IV Design Example 4. Serial Lite IV Intel® Agilex™ FPGA IP Design Example User Guide Archives 5. Document Revision History for the Serial Lite IV Intel® Agilex® FPGA IP Design Example User Guide
2. Quick Start Guide x
2.1. Design Example Block Diagram 2.2. Hardware and Software Requirements 2.3. Generating the Design 2.4. Compiling and Simulating the Design 2.5. Compiling and Testing the Design
2.3. Generating the Design x
2.3.1. Design Example Parameters 2.3.2. Directory Structure
3. Detailed Description for Serial Lite IV Design Example x
3.1. Features 3.2. Design Example Components 3.3. Simulation 3.4. Hardware Testing 3.5. Error Handling 3.6. Link Debugging Sequence 3.7. Serial Lite IV IP Toolkit
3.2. Design Example Components x
3.2.1. Traffic Generator 3.2.2. Traffic Checker 3.2.3. DCFIFO
3.3. Simulation x
3.3.1. Simulation Results for Basic Mode 3.3.2. Simulation Result for Full Mode
3.4. Hardware Testing x
3.4.1. Hardware Testing Result for Basic Transfer Mode 3.4.2. Hardware Testing Result for Full Transfer Mode 3.4.3. Traffic Statistic Results
3.7. Serial Lite IV IP Toolkit x
3.7.1. Setting Up and Running the Toolkit 3.7.2. Toolkit GUI Settings
1. About the Serial Lite IV Intel® Agilex™ FPGA IP Design Example User Guide
2. Quick Start Guide
3. Detailed Description for Serial Lite IV Design Example
4. Serial Lite IV Intel® Agilex™ FPGA IP Design Example User Guide Archives
5. Document Revision History for the Serial Lite IV Intel® Agilex® FPGA IP Design Example User Guide

3. Detailed Description for Serial Lite IV Design Example

This design example demonstrates the functionality of data streaming using basic and full mode.

You can specify the parameter settings of your choice and generate the design example.

The design example is available only in duplex mode.

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