2.5. Compiling and Testing the Design
Follow these steps to compile and test the design in hardware:
- Launch the Intel® Quartus® Prime Pro Edition software and change the directory to example_design_dir/ed_synth/ and open the seriallite_iv_streaming_demo.qpf file.
- Click Processing> Start Compilation to compile the design.
The Intel® Quartus® Prime Pro Edition software automatically loads the timing constraints for the design example and the design components during compilation.
- Connect the development board to the host computer.
- Configure the FPGA on the development board using the generated seriallite_iv_streaming_demo.sof file (Tools> Programmer).
The design example targets the Intel® Agilex™ F-Series Transceiver SoC Development Kit.
The design includes a Synopsys Design Constraints File (.sdc) and an Intel® Quartus® Prime Pro Edition Settings File (.qsf) with verified constraints in loopback mode. If you use the design example with another device or development board, you may need to update the device settings and constraints in the .qsf file.Note: Before downloading the design onto the FPGA, you need to program the clock oscillator on the board to match the transceiver PLL and IOPLL reference clock frequencies configured in the design example. Refer to the Intel® Agilex™ F-Series Transceiver SoC Development Kit User Guide: Control on-board clock through Clock Controller GUI for steps to program the clock oscillator on board.
- After loading the .sof file onto the development board, you can run the hardware design example using either system console or the Serial Lite IV IP toolkit. For more information about the Serial Lite IV IP toolkit, refer to the Serial Lite IV IP Toolkit topic.