Serial Lite IV Intel® Agilex™ FPGA IP Design Example User Guide

ID 683391
Date 11/01/2021
Public

2.4. Compiling and Simulating the Design

The design example testbench simulates your generated design.
  1. Change the working directory to <example_design_directory>/ed_sim/<simulator>
    Note: In Serial Lite IV Intel® FPGA IP version 1.1.0, the ModelSim* simulator does not capture the top-level IP signals in the waveform. To capture the top-level IP signals, add the ld_debug command to the ed_sim/mentor/run_tb.tcl file.
  2. Run the simulation script for the simulator of your choice.
    Table 6.  Testbench Simulation Scripts
    Simulator File Directory Command
    ModelSim*
    Note: This IP only supports ModelSim* - Intel® FPGA Starter Edition simulator.
    <variation name>seriallite4_0_example_design/ed_sim/mentor do run_tb.tcl
    QuestaSim*
    VCS* <variation name>seriallite4_0_example_design/ed_sim/synopsys/vcs sh run_tb.sh
    VCS* MX <variation name>seriallite4_0_example_design/ed_sim/synopsys/vcsmx sh run_tb.sh
    Xcelium* <variation name>seriallite4_0_example_design/ed_sim/xcelium sh run_tb.sh
  3. When the simulation is complete, you can now analyze the results and verify the design. A successful simulation ends with the following message, "Test Passed."
#    ****************************** Data Forwarding Test Completed ****************************
#    
#    ************************************** Test Completed ************************************
#    
#    End time                       = 534579600
#    
#    Total words tranferred         = 10000
#    
#    Number of bursts               = 0
#    
#    Random number generator seed   = 1756255697
#    
#    Link Latency                   = 434 ns
#    
#    *************************************** Test Passed **************************************

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