Fault Injection Intel® FPGA IP Core User Guide

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ID 683254
Date 7/09/2019
Public
Document Table of Contents
Document Table of Contents x
1. Fault Injection Intel® FPGA IP Core User Guide
1. Fault Injection Intel® FPGA IP Core User Guide x
1.1. Features 1.2. Device Support 1.3. Resource Utilization and Performance 1.4. Installing and Licensing Intel® FPGA IP Cores 1.5. Customizing and Generating IP Cores 1.6. Functional Description 1.7. Using the Fault Injection Debugger and Fault Injection IP Core 1.8. Fault Injection IP Core User Guide Archives 1.9. Document Revision History for Fault Injection IP Core User Guide
1.5. Customizing and Generating IP Cores x
1.5.1. IP Catalog and Parameter Editor 1.5.2. IP Core Generation Output ( Intel® Quartus® Prime Pro Edition)
1.6. Functional Description x
1.6.1. Single Event Upset Mitigation 1.6.2. Fault Injection IP Pin Description
1.7. Using the Fault Injection Debugger and Fault Injection IP Core x
1.7.1. Instantiating the Fault Injection IP Core 1.7.2. Defining Fault Injection Areas 1.7.3. Using the Fault Injection Debugger 1.7.4. Command-Line Interface
1.7.1. Instantiating the Fault Injection IP Core x
1.7.1.1. About the EMR Unloader IP Core 1.7.1.2. About the Advanced SEU Detection IP Core
1.7.2. Defining Fault Injection Areas x
1.7.2.1. Performing Hierarchy Tagging 1.7.2.2. About SMH Files
1.7.3. Using the Fault Injection Debugger x
1.7.3.1. Hardware and Software Requirements 1.7.3.2. Configuring Your Device and the Fault Injection Debugger 1.7.3.3. Constraining Regions for Fault Injection 1.7.3.4. Specifying Error Types 1.7.3.5. Injecting Errors 1.7.3.6. Recording Errors 1.7.3.7. Clearing Injected Errors
1.7.4. Command-Line Interface x
1.7.4.1. Targeted Fault Injection Feature 1.7.4.2. Advanced Command-Line Options: ASD Regions and Error Type Weighting
1.7.4.1. Targeted Fault Injection Feature x
1.7.4.1.1. Specifying an Error List From the Command Line 1.7.4.1.2. Specifying an Error List From Prompt Mode 1.7.4.1.3. Determining CRAM Bit Locations
1. Fault Injection Intel® FPGA IP Core User Guide

1.6.1. Single Event Upset Mitigation

Integrated circuits and programmable logic devices such as FPGAs are susceptible to SEUs. SEUs are random, nondestructive events, caused by two major sources: alpha particles and neutrons from cosmic rays. Radiation can cause either the logic register, embedded memory bit, or a configuration RAM (CRAM) bit to flip its state, thus leading to unexpected device operation.

Intel® Arria® 10, Intel® Cyclone® 10 GX, Arria® V, Cyclone® V, Stratix® V and newer devices have the following CRAM capabilities:

  • Error Detection Cyclical Redundance Checking (EDCRC)
  • Automatic correction of an upset CRAM (scrubbing)
  • Ability to create an upset CRAM condition (fault injection)

For more information about SEU mitigation in Intel FPGA devices, refer to the SEU Mitigation chapter in the respective device handbook.

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