Fault Injection Intel® FPGA IP Core User Guide

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ID 683254
Date 7/09/2019
Public
Document Table of Contents

1.6.2. Fault Injection IP Pin Description

The Fault Injection IP core includes the following I/O pins.

Table 4.   Fault Injection IP Core I/O Pins

Pin Name

Pin Direction

Pin Description

crcerror_pin

input

Input from Error Message Register Unloader Intel® FPGA IP (EMR Unloader IP). This signal is asserted when a CRC error has been detected by the device's EDCRC.

emr_data input

Error Message Register (EMR) contents. Refer to the appropriate device handbook for the EMR fields.

This input complies with the Avalon Streaming data interface signal.

emr_valid

input

Indicates the emr_data inputs contain valid data. This is an Avalon Streaming valid interface signal.
Reset

input

Module reset input. The reset is fully controlled by the Fault Injection Debugger.

error_injected

output

Indicates an error was injected into CRAM as commanded via the JTAG interface. The length of time this signal asserts depends on your settings of the JTAG TCK and control block signals. Typically, the time is around 20 clock cycles of the TCK signal.

error_scrubbed

output

Indicates the device scrubbing is complete as commanded via the JTAG interface. The length of time this signal asserts depends on your settings of the JTAG TCK and control block signals. Typically, the time is around 20 clock cycles of the TCK signal.

intosc

output

Optional output. The Fault Injection IP uses this clock, for example, to clock the EMR_unloader block.
Figure 4.  Fault Injection IP Pin Diagram

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