1.1. Features 1.2. Device Support 1.3. Resource Utilization and Performance 1.4. Installing and Licensing Intel® FPGA IP Cores 1.5. Customizing and Generating IP Cores 1.6. Functional Description 1.7. Using the Fault Injection Debugger and Fault Injection IP Core 1.8. Fault Injection IP Core User Guide Archives 1.9. Document Revision History for Fault Injection IP Core User Guide
22.214.171.124.3. Determining CRAM Bit Locations
When the Fault Injection Debugger detects a CRAM EDCRC error, the Error Message Register (EMR) contains the syndrome, frame number, bit location, and error type (single, double, or multi-bit) of the detected CRAM error.
During system testing, save the EMR contents reported by the Fault Injection Debugger when you detect an EDCRC fault.
Note: With the recorded EMR contents, you can supply the frame and bit numbers to the Fault Injection Debugger to replay the errors noted during system testing, to further design, and characterize a system recovery response to that error.