Intel® Quartus® Prime Pro Edition User Guide: Timing Analyzer

ID 683243
Date 10/02/2023

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

3.6.2. SDC File Precedence

You must add any .sdc file that you create to the project to be read during fitting and timing analysis. The Fitter and the Timing Analyzer process .sdc files in the order they appear in the .qsf. If no .sdc appears in the .qsf, the Intel® Quartus® Prime software searches for an .sdc with the name <current revision>.sdc in the project directory.
Note: Intel® FPGA IP packages RTL and the SDC constraints for the IP within a single .ip file. Therefore, within a project's .qsf there may be references to SDC constraints packaged with the containing .ip file.
Figure 93. .sdc File Order of Precedence

Click Settings > Timing Analyzer to add, remove, or change the processing order of .sdc files in the project, as Step 1: Specify Timing Analyzer Settings describes.

If you use the Intel® Quartus® Prime Text Editor to create an .sdc file, the option to Add file to the project enables by default when you save the file. If you use any other editor to create an .sdc file, you must add the file to the project.

The .sdc file must contain only timing constraint commands. Tcl commands to manipulate the timing netlist or control the compilation must be in a separate Tcl script.

Note: If you type the read_sdc command at the command line without any arguments, the Timing Analyzer reads constraints embedded in HDL files, then reads the .sdc files following the .sdc file precedence order.