- Updated compilation dashboard image in Step 3: Run the Timing Analyzer.
- Revised the following topics entirely:
- Using Entity-bound SDC Files
- Entity-bound Constraint Scope
- Entity-bound Constraint Examples
- Corrected typo in command example in Report Data Delay topic.
- Corrected typo in command example in Constraining CDC Paths topic.
- Corrected typo in command example in Maximum Skew topic.
- Added Promoting Critical Warnings to Errors topic.
- Revised updated image and description in Report Register Description for new Without a Control Signal and Synchronous Load columns and data.
- Revised outdated timing model descriptions in Setting the Operating Conditions for Timing Analysis topic.
- Renamed the report title "Report Reset Statistics" as "Report Register Statistics."
- Revised the Report Register Statistics topic to describe some new features of the report.
- Revised Report Fmax Summary topic to refer to get_clock_fmax_info command and provide more detail.
- Revised Example SDC Constraints for External Clock Mux to replace logically_exclusive with physically_exclusive.
- Described new Clock Network Viewer in Report Clocks and Clock Networks topic.
- Updated Report Register Spread topic for new angle and area spread types and -to_clock filtering.
- Added new Report Timing By Source Files topic.
- Added new Report Metastability topic.
- Added new Report Bottlenecks topic.
- Added new Specifying Custom Bottleneck Criteria topic.
- Revised Basic .sdc Constraints Example in Example Circuit and SDC File topic.
- Added more detailed constraint example and diagram to Set Clock Groups topic.
- Revised scripting examples and screenshots in Correlating Constraints to the Timing Report topic.
- Revised scripting example in Creating Base Clocks topic.
- Revised scripting example in Clock Divider Example topic.
- Revised Constraining CDC Paths topic.
- Added note about referenced SDCs within IP to SDC File Precedence topic.
- Updated name of Report Hierarchical Retiming Restrictions command and report to Report Retiming Restrictions.
- Added Constraining CDC Paths topic and linked to related topics.
- Updated Setting the Operating Conditions with details about operating condition nomenclature.
- Replaced Custom Reports, Device Specific, Diagnostic, and Slack report folder names throughout.
- Added Report Exceptions and Exceptions Reachability topic describing new report.
- Added Report Clocks and Clock Networks topic describing new report.
- Added Report Data Delay topic describing report.
- Mentioned option to view multiple before and after paths in Report Neighbor Paths topic.
- Added set_clock_groups to Timing Exception Precedence
- Updated content of Extra Info tab in Report Timing topic.
- Corrected the set_clock_groups -group A -group B table in the Creating Clock Groups topic.
- Removed Report Custom CDC Viewer Command topic.
- Revised assignment examples in Exclusive Clock Groups topic.
- "Report Reset Statistics"
- "Report Asynchronous CDC"
- Two new fields to "Report Pipelining Information".
- New screenshots to "Report Logic Depth" and "Report Neighbor Paths"
- get_registers and get_keepers to "Collection Commands".
- Removed -include and -exclude options from "Maximum Skew"
||Added extra SDC_ENTITY_FILE info to "Using Entity-bound SDC Files"
- Added "Cross Probing with Design Assistant" section.
- Updated “Step 3: Run the Timing Analyzer” for multiple methods.
- Updated "Step 1: Specify Timing Analyzer Settings for new tabbed dialog box and options.
- Added new "Report Register Spread," "Report Route Net of Interest," "Report Hierarchical Retiming Restrictions," and "Report Pipelining Information" topics.
- Updated "Report Clock Transfers" topic for new data columns.
- Updated "Report Timing" topic for Extra Info tab data.
- Updated "Report Fmax Summary," "Report Logic Depth," "Report Neighbor Paths," "Report CDC Viewer," and "Report Custom CDC Viewer" topics for latest GUI and consistency.
- Added details and Intel Agilex® 7 device examples to "Setting the Operating Conditions" topic.
- Added "Report Logic Level Depth" topic.
- Added "Report Neighbor Paths" topic.
- Added "Enabling Time Borrowing Optimization" topic.
- Added "Report Time Borrowing Data" topic.
- Updated "Setting Operating Conditions" for SmartVID timing models.
- Added step for setting operating conditions to "Step 4: Run Timing Analysis."
- Added details about exclusive paths to "Maximum Skew" topic.
- Added GUI steps for creating entity-bound SDC files to "Using Entity-bound SDC Files" topic.
- Corrected typo in "Timing Constraint Precedence" topic.
- Corrected typo in "Maximum Skew" topic.
- Updated "Viewing Design Assistant Recommendations" for latest GUI changes.
- Improved description and diagram for "Exclusive Clock Groups" topic.
- Added "Using Entity-bound SDC Files" topic.
- Added "Scoping Entity-bound Constraints" topic.
- Added "Entity-bound Constraint Examples" topic.
- Revised "Basic Timing Analysis Flow" section to add sequential step organization, update steps, and add supporting screenshots.
- Added Timing Analyzer screenshot to "Using the Timing Analyzer" topic.
- Removed "Creating a Constraint File from Templates with the Text Editor" topic due to limitations of this feature in this version of the software.
- Retitled "SDC Constraint Creation Summary" to " Dual Clock SDC Example."
- Retitled "Default Settings" to "Default Multicycle Analysis."
- Retitled "SDC (Clock and Exception) Assignments on Blackbox Ports" to "Constraining Design Partition Ports."
- Added "Viewing Design Assistant Recommendations" topic.
- First release as part of the stand-alone Timing Analyzer User Guide
- Removed outdated figure: Design Flow with the Timing Analyzer.
- Updated Performing an Initial Analysis and Synthesis topic with Intel® Quartus® Prime Pro Edition commands.
- Updated Using Fitter Overconstraints topic for Intel® Stratix® 10 support.
- Added Using Fitter Overconstraints topic.
- Added Clock Domain Crossing report topics
- Implemented Intel rebranding.
- Added support for -blackbox option with set_input_delay, set_output_delay, remove_input_delay, remove_output_delay.
||Added new topic: SCDS (Clock and Exception) Assignments on Blackbox Ports
- Changed instances of Quartus II to Quartus Prime.
- Added a description of running three- and four-corner analysis with --mode=implement|finalize.
- Added description for new set_operating_conditions UI.
||Added and updated contents in support of new timing algorithms for Arria 10:
- Enhanced Timing Analysis for Arria 10
- Maximum Skew (set_max_skew command)
- Net Delay (set_net_delay command)
- Create Generated Clocks (clock-as-data example)
||Major reorganization. Revised and added content to the following topic areas:
- Timing Constraints
- Create Clocks and Clock Constraints
- Creating Generated Clocks
- Creating Clock Groups
- Clock Uncertainty
- Running the Timing Analyzer
- Generating Timing Reports
- Understanding Results
- Constraining and Analyzing with Tcl Commands
||Added command line compilation requirements for Arria 10 devices.
- Minor updates.
- Updated format.
- Removed HardCopy device information.
- Reorganized chapter.
- Added “Creating a Constraint File from Intel® Quartus® Prime Templates with the Intel® Quartus® Prime Text Editor” section on creating an SDC constraints file with the Insert Template dialog box.
- Added “Identifying the Intel® Quartus® Prime Software Executable from the SDC File” section.
- Revised multicycle exceptions section.
- Consolidated content from the Best Practices for the Intel® Quartus® Prime Timing Analyzer chapter.
- Changed to new document template.
- Updated to improve flow. Minor editorial updates.
- Changed to new document template.
- Revised and reorganized entire chapter.
- Linked to Intel® Quartus® Prime Help.
||Updated to link to content on SDC commands and the Timing Analyzer GUI in Intel® Quartus® Prime Help.
||Updated for the Intel® Quartus® Prime software version 9.1, including:
- Added information about commands for adding and removing items from collections
- Added information about the set_timing_derate and report_skew commands
- Added information about worst-case timing reporting
- Minor editorial updates
||Updated for the Intel® Quartus® Prime software version 8.1, including:
- Added the following sections:
“set_net_delay” on page 7–42
“Annotated Delay” on page 7–49
“report_net_delay” on page 7–66
- Updated the descriptions of the -append and -file < name > options in tables throughout the chapter
- Updated entire chapter using 8½” × 11” chapter template
- Minor editorial updates