184.108.40.206.7. Source Clock Frequency is a Multiple of the Destination Clock Frequency
In the following example the source clock frequency is a multiple of the destination clock frequency:
The following timing diagram shows the default setup check analysis the Timing Analyzer performs:
The setup relationship demonstrates that the data launched at edge one does not require capture, and the data launched at edge two requires capture; therefore, you can relax the setup requirement. To correct the default analysis, you shift the launch edge by one clock period with a start multicycle setup exception of two. The following multicycle exception adjusts the default analysis in this example:
set_multicycle_path -from [get_clocks clk_src] -to [get_clocks clk_dst] \ -setup -start 2
The following timing diagram shows the preferred setup relationship for this example:
The following timing diagram shows the default hold check analysis the Timing Analyzer performs for a start multicycle setup value of two:
In this example, the hold check two is too restrictive. The data is launched next by the edge at 10 ns and must check against the data captured by the current latch edge at 10 ns, which does not occur in hold check two. To correct the default analysis, you use a start multicycle hold exception of one.