188.8.131.52.3. Accounting for a Phase Shift (-phase)
For example, the following code phase-shifts one output of a PLL forward by a small amount, in this case 0.2 ns.
Cross Domain Phase-Shift
create_generated_clock -source pll|inclk -name pll|clk pll|clk create_generated_clock -source pll|inclk -name pll|clk -phase 30 pll|clk
The default setup relationship for this phase-shift is 0.2 ns, shown in Figure A, creating a scenario where the hold relationship is negative, which makes achieving timing closure nearly impossible.
The following constraint allows the data to transfer to the following edge:
set_multicycle_path -setup -from [get_clocks clk_a] -to [get_clocks clk_b] 2
The hold relationship derives from the setup relationship, making a multicycle hold constraint unnecessary.