Intel® Quartus® Prime Pro Edition User Guide: Timing Analyzer

ID 683243
Date 10/02/2023

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2.2.2. Clock Setup Analysis

To perform a clock setup check, the Timing Analyzer determines a setup relationship by analyzing each launch and latch edge for each register-to-register path.

For each latch edge at the destination register, the Timing Analyzer uses the closest previous clock edge at the source register as the launch edge. The following figure shows two setup relationships, setup A and setup B. For the latch edge at 10 ns, the closest clock that acts as a launch edge is at 3 ns and has the setup A label. For the latch edge at 20 ns, the closest clock that acts as a launch edge is 19 ns and has the setup B label. The Timing Analyzer analyzes the most restrictive setup relationship, in this case setup B; if that relationship meets the design requirement, then setup A meets the requirement by default.

Figure 7. Setup Check

The Timing Analyzer reports the result of clock setup checks as slack values. Slack is the margin by which a circuit meets or does not meet the timing requirement. Positive slack indicates the margin by the circuit meets the requirement. Negative slack indicates the margin by which the circuit does not meet the requirement.

Figure 8. Clock Setup Slack for Internal Register-to-Register Paths

The Timing Analyzer performs setup checks using the maximum delay when calculating data arrival time, and minimum delay when calculating data required time. Some of the spread between maximum arrival path delays and minimum required path delays may be recoverable with path pessimism removal, as Timing Pessimism describes.

Figure 9. Clock Setup Slack from Input Port to Internal Register
Figure 10. Clock Setup Slack from Internal Register to Output Port