Intel® Quartus® Prime Pro Edition User Guide: Timing Analyzer

ID 683243
Date 10/02/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

3.6.5. Creating Clocks and Clock Constraints

You must define all clocks and any associated clock characteristics, such as uncertainty, latency or skew. The Timing Analyzer supports .sdc commands that accommodate various clocking schemes, such as:

  • Base clocks
  • Virtual clocks
  • Multifrequency clocks
  • Generated clocks