220.127.116.11. Report Register Statistics
- This report works similarly in both post-synthesis (DNI flow) and post-plan timing analysis. However, the report's Without a Clock column is more helpful for the post-synthesis timing analysis because conventional (non-SDC-on-RTL) SDCs are not typically loaded in the post-synthesis mode, so through this report, you can analyze how timing gets affected in the absence of the SDCs.
- Clocks generated from derive_clocks commands do not count as user clocks.
- The report's Without a Control Signal column identifies registers that have no corresponding control signal.
- The report's Synchronous Load column identifies any synchronous load that can apply to Intel® Arria® 10 devices only.
The Without a Clock column informs you of the number of registers where no defined clock feeds the registers in the hierarchy shown in the Register Count column. A value of 0 in this column suggests that your design has SDC-defined clocks feeding registers in the design. The Unique Clocks column indicates the number of unique SDC-defined clocks feeding registers in the hierarchy identified by the Register Count. To view these columns, enable Show registers without clocks and Show the number of unique clocks feeding registers additional options in the dialog that displays when you run the report, as shown in the following image: