Intel® Quartus® Prime Pro Edition User Guide: Timing Analyzer

ID 683243
Date 10/02/2023

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Document Table of Contents Constraining CDC Paths

It is essential to apply timing constraints to the multibit clock domain crossing (CDC) paths in your design. You can use the following constraints to constrain CDC paths:

Attention: As of Intel® Quartus® Prime Pro Edition software version 21.3, the set_false_path constraint does not override the set_max_skew constraint. You can now apply the set_false_path and set_max_skew constraints on the same path without override.
Table 28.  CDC Path Constraints
Constraints Description


set_clock_groups -asynchronous

Both constraints prevent the Compiler from optimizing slack between asynchronous domain crossings. set_clock_groups is the most aggressive constraint.

  • Clock-based false paths are less aggressive because these constraints only cut timing on the from_clock to to_clock order specified.
  • Clock-based false paths are unlike clock groups that cut the path in both directions.
  • Path-based false paths are the most specific constraint because they cut only on the specified from and to nodes.
set_max_skew Sets a bound on the allowable skew between different bus bits.
  • Check the timing of your clock domain crossing by running the Report Max Skew Summary command.
  • The actual skew requirements depends on your design characteristics, and how you handle the clock domain crossing.

set_net_delay -max


Sets a bound on the allowable datapath delay on any bit of a bus transfer.

  • set_net_delay is for constraining individual clock edges and nets. Run the Report Net Delay Summary command to report data for this constraint.
  • set_data_delay is for constraining entire paths. Run the Report Data Delay command to report data for this constraint.

The following shows example constraints for a clock domain crossing between data_a in clock domain clk_a, and data_b in clock domain clk_b:

create_clock -name clk_a -period 4.000 [get_ports {clk_a}]
create_clock -name clk_b -period 4.500 [get_ports {clk_b}]
set_clock_groups -asynchronous -group [get_clocks {clk_a}] -group \
     [get_clocks {clk_b}]
set_net_delay -from [get_registers {data_a[*]}] -to [get_registers \
     {data_b[*]}] -max -get_value_from_clock_period \
     dst_clock_period -value_multiplier 0.8
set_max_skew -from [get_keepers {data_a[*]}] -to [get_keepers \
     {data_b[*]}] -get_skew_value_from_clock_period min_clock_period \
     -skew_value_multiplier 0.8

The following examples show applying set_false_path for a design that contains a DCFIFO block to avoid timing failures in the synchronization registers. These examples are for constraining single-bit synchronizer CDC paths:

  • For paths crossing from the write into the read domain, apply a false path assignment between registers delayed_wrptr_g and rs_dgwp:
    set_false_path -from [get_registers {*dcfifo*delayed_wrptr_g[*]}] \
    -to [get_registers {*dcfifo*rs_dgwp*}]
  • For paths crossing from the read into the write domain, apply a false path assignment between registers rdptr_g and ws_dgrp:
    set_false_path -from [get_registers {*dcfifo*rdptr_g[*]}] \
    -to [get_registers {*dcfifo*ws_dgrp*}]