184.108.40.206.5. Destination Clock Frequency is a Multiple of the Source Clock Frequency
The following example shows a design in which the destination clock frequency is a multiple of the source clock frequency.
The following timing diagram shows the default setup check analysis that the Timing Analyzer performs:
The setup relationship demonstrates that the data requires capture at edge two; therefore, you can relax the setup requirement. To correct the default analysis, you shift the latch edge by one clock period with an end multicycle setup exception of two. The following multicycle exception assignment adjusts the default analysis in this example:
set_multicycle_path -from [get_clocks clk_src] -to [get_clocks clk_dst] \ -setup -end 2
The following timing diagram shows the preferred setup relationship for this example:
The following timing diagram shows the default hold check analysis the Timing Analyzer performs with an end multicycle setup value of two.
In this example, hold check one is too restrictive. The data is launched by the edge at 0 ns and must check against the data captured by the previous latch edge at 0 ns, which does not occur in hold check one. To correct the default analysis, you must use an end multicycle hold exception of one.